jleahy

19 ms·

181.
by jleahy 6y ago
For a tad more money you can get a TWSBI Eco, that would be my recommendation. A very nice pen, not fancy at all but very practical.
182.
by jleahy 6y ago
I’m guessing they are going to try and raise the prices and create a new market segment. Just as they have separated datacenter GPUs, increased the price massively (coming up to a factor of 10x) and then tried to use a stick to prevent the
183.
by jleahy 6y ago
They're not only unsafe, but as far as I'm aware they're a compiler implementation detail that isn't really supposed to be used in user code (along with rustc_nonnull_optimization_guaranteed). It's actually how NonZ
184.
by jleahy 6y ago
Sure, but SPI is basically a parallel bus that's 1-bit wide. It has all the hallmarks (separate clock and single-ended signaling), so adding extra bits was an easy thing.
185.
by jleahy 6y ago
It's really about b/c rather than a, and it's not really about 'serial', it's about having differential signaling, an embedded clock (eg. 8B10B coding) and having multiple lanes that tolerate a length mismatch
186.
by jleahy 6y ago
Well some laptops come with an option of an 'm3', 'i5' or 'i7'. On the internet you'll see lots of people saying the the i5 will crush the m3, however all of those three processors are identical with only
187.
by jleahy 6y ago
And I have the 'SE 2', which they just refer to as 'SE' in their marketing despite the fact they already had a different product with the same name.
188.
by jleahy 6y ago
Even after making absolute worst case assumptions (linear no threshold), which are still widely debated (see the book ‘Radiation and reason’ by Wade Allison, my old professor, if you are sufficiently interested).
189.
by jleahy 6y ago
You can do the pre-rendering on the previous line if you can spare two buffers. You just render into a buffer, then during the blanking interval latch it into a shift register. That gives you a lot more time to render.
190.
by jleahy 6y ago
Does a depth prepass not avoid this?
191.
by jleahy 6y ago
Personally I never noticed that there is a logo, and that logo means up. And I’ve plugged in a lot of USB cables in my time, and even read parts of the USB spec in order to implement USB. Maybe I’m just a moron though.
192.
by jleahy 6y ago
Ah Sub7... a single tear runs down my cheek
193.
by jleahy 6y ago
I once wrote a piece of software that cracked passwords for Windows 9x network shares. It looked just like the movies, it would crack one letter of the password at a time, each letter would cycle through the possibilities and then lock in,
194.
by jleahy 6y ago
Or just didn’t go out of your way to do things in a way that’s both more difficult and slower.
195.
by jleahy 6y ago
I guess my comment about 16 registers being enough was more in the context of low power. In benchmarks I've seen going from 8->16 is a big boost, but going from 16->32 is generally only a few %. In ARM64 32 is definitely the righ
196.
by jleahy 6y ago
Yes but there are no convenient charging points, if the battery runs out then you need to replace it, not charge it. All the more reason to throw used batteries away (they’re cheap and it’s less to carry).
197.
by jleahy 6y ago
Or have wings.
198.
by jleahy 6y ago
That's because of the energy density (per mass) of Li-Ion batteries. You basically hit a wall at 20 minutes that's very hard to push past (it almost feels like a law of physics). But maybe they're using non-rechargeable batte
199.
by jleahy 6y ago
> Flags don't have to add an extra implicit input/output everywhere. Both ARM and PowerPC avoid updating the flags unless explicitly requested. Well ultimately they do, not updating the flags means more options for the compiler
200.
by jleahy 6y ago
Right, but the OP and most of HN seem to believe that RISC-V is some magic thing that is going to beat M1/Zen/whatever one day while also providing amazingly low power for tiny 32-bit cores. Also, RISC-V is also essentially split
201.
by jleahy 6y ago
> Has anyone quantified the penalty in using register renaming to allow for a split register file in high-performance implementations while allowing compatible low-power implementations with a single register file? Maybe the transistor s
202.
by jleahy 6y ago
I think it’s smart, most branches are short and almost all important branches are short (eg. loops). The flags register adds an extra implicit input/output everywhere, and renaming is expensive enough without that. However given they a
203.
by jleahy 6y ago
I am a hardware designer. See my comment above, it's going to be ugly. Fast adders are still slow (and awkward), but they only have to propagate a single bit of information, this is much messier. As a side-note carry-skip doesn't
204.
by jleahy 6y ago
Macro-op fusion is something that is really quite painful to implement in the front-end. Essentially once you have both macro-op fusion and potentially multiple micro-ops for a single instruction you have fully variable length instructions.
205.
by jleahy 6y ago
That was true in the past, but at least for me Steam Proton has completely removed my need to use Windows for games. It’s a point where you can apply aforementioned anvil (something I frequently make use of) and just not buy/play any g
206.
by jleahy 6y ago
I think (1) potentially has a place for cases where it’s supposed to be background music that you wouldn’t really pay attention to (but shouldn’t repeat). It’s pretty easy to take a style of music and produce something that sort of goes rou
207.
by jleahy 6y ago
The dirty secret is that you can't really make a transistor much smaller than about 30nm. The contacted gate pitch (for all intents and purposes this is the 'size' of a transistor) actually only decreased 50% from 28nm to 7nm
208.
by jleahy 6y ago
No, faster than light needs negative energies.
209.
by jleahy 6y ago
The argument is that they're impossible, because they require negative energy (which not only doesn't exist but doesn't make sense), so it's fine. In the presence of negative energy you can form closed time-like curves i
210.
by jleahy 6y ago
Even more importantly, and I'm surprised you didn't mention it, static compile time VLIW doesn't know what to do for memory access. A load might take any number of cycles depending on whether the line is in L1, L2 or L3 cache

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