It's really about b/c rather than a, and it's not really about 'serial', it's about having differential signaling, an embedded clock (eg. 8B10B coding) and havi

It's really about b/c rather than a, and it's not really about 'serial', it's about having differential signaling, an embedded clock (eg. 8B10B coding) and having multiple lanes that tolerate a length mismatch (and realigning them dynamically using some kind of marker in the data). You can have any one of those three things and get some of the benefits. Note that one thing that isn't special is having 1 lane, and in fact few 'serial' protocols (eg. PCIe) actually use 1 lane. If you think about PCIe we moved from a 32-bit bus (32 wires bidirectional) to x16 slots with 64 wires in total (16 lanes, 2 directions each, +ve/-ve for each). Maybe you consider AGP as the true precursor of x16 PCIE, but that was also 32 I/O lanes. So there wasn't a wire saving. The truth is if you want very high data rates over medium or long distances then you have to go with 'serial' (the three points above) and you can get anywhere between 2.5Gbps and 54Gbps per differential pair depending on the technology. If you are willing to have shorter distances then you can get up to something like 6.4Gbps per pin and it'll use less power (vastly less power if the data rate goes down to <1Gbps per pin), but you won't be able to reach as far. Technologies like HBM use single-ended (non-differential) signaling and make up for this with huge amounts of very short wires (up to a thousand or so). Given the constraints of the technology if I was designing RAM right now with no legacy baggage I'd chose single-ended signaling, and if I was designing a high-speed I/O slot I would choose differential signaling. So it's all quite sensible and rational.