inforichland

4 ms·

1.
by inforichland 11y ago
Exactly, that's how I would (hopefully will soon) implement it as well; it takes a few extra cycles but avoids extra overhead.
2.
by inforichland 11y ago
I am still leery of the "unconventional" HDLs. I don't really see many of them as much of an improvement over say, VHDL-2008; you get records and functions and instantiation is not as verbose. Yes, the language is a little
3.
by inforichland 11y ago
Thank you :) Also thanks for the information; I had been wondering if someone had made some more thorough automated tests, I will definitely check those out!
4.
Show HN: A pipelined RISC-V processor written in VHDL(github.com)
65 points by inforichland 11y ago|29 comments
5.
by inforichland 12y ago
Honestly, I'm still on the new-ish end of FPGA design (a year or so), so I'm probably not qualified to answer the first one, but I'd have to guess probably not much faster? A fully pipelined CPU could theoretically achieve t
6.
by inforichland 12y ago
Yes, I have seen it, and I have used it a few times. For some types of modules, I really do like how it separates out the state from the logic itself; as a person who started writing firmware first, and then started logic design, the two-p
7.
by inforichland 12y ago
Most likely it would be faster, as the Forth primitive words are implemented in hardware. The single-cycle words are: +, -, 2*, 2/, dup, not, @, !, >r, drop, r>, rot, -rot, swap, nip, tuck, over, =. Un/conditional jumps an
8.
by inforichland 12y ago
I guess the unstated goal of this was to create a small, simple and fast soft-core processor that could be used to augment FPGA designs (<15% of a small devices resources @ 100MHz). Honestly, I wrote this just to scratch an itch. I&#x27
9.
Show HN: A 16-bit Forth machine written in VHDL(github.com)
80 points by inforichland 12y ago|16 comments