howerj

9 ms·

61.
by howerj 6y ago
That looks like it might work, thank you. My search did not find this.
62.
by howerj 6y ago
I have noticed there are quite a few FAT-32 implementations out there, but none that do what I want. Ideally what I want is something that would do the following; allow the creation of a new FAT-32 image file of a specified length given a t
63.
by howerj 6y ago
Thanks! Making the initial (working) version of the CPU was fairly easy, however I wanted to do more than just write in low-level assembly and blink lights on and off, so keeping the system small whilst being able to support a higher level
64.
by howerj 6y ago
I do not think I could give an accurate conversion between FPGA Slices and transistors myself, it is certainly small (23 slices) and processors with similar capabilities ran in thousands of transistors/tubes range. You should look into
65.
by howerj 6y ago
Not really, I was only inspired by their existence and nothing else, in retrospect it might have been nice to copy the instruction set of something like a PDP8-S and get software for one of them running on it, but I like having something th
66.
by howerj 6y ago
Hello HN, here is a project that I have recently finished, it is a very niche CPU written in VHDL and verified to work on an [FPGA][]. It is a 16-bit [bit-serial][] CPU, which means the processor is incredibly slow taking 102 clock cycle
67.
Show HN: Bit Serial CPU(github.com)
99 points by howerj 6y ago|17 comments
68.
by howerj 6y ago
Hello HN, here is a project that I have recently finished, it is a very niche CPU written in VHDL and verified to work on an [FPGA][]. It is a 16-bit [bit-serial][] CPU, which means the processor is incredibly slow taking 102 clock cycle
69.
Show HN: Bit Serial CPU(github.com)
6 points by howerj 6y ago|2 comments
70.
by howerj 6y ago
This is great! I can imagine this repository will be quite popular as it feeds into the developers ego (including mine). I wonder how much development is not fueled by ideals about giving back but instead about chasing stars. Edit: Removed
71.
by howerj 8y ago
That's great, raise or ticket or send me an email if you find anything useful. It's not too much work for me to convert things into a usable format if I have a BDF file (8x12 only - anything else would require hardware changes!) f
72.
by howerj 8y ago
Hi! Sorry, I've been at work all day... The VGA module on which the VT-100 is built around used that font (I am not sure of its name - I guess "MDA/VGA font" would do). That VGA module came from here: http://w
73.
by howerj 8y ago
I have a background in electronic engineering, and did a fair bit of digital design related courses so large bits of it were in my skill-set, but mainly work with C in an embedded context. This project has been going on for years, but I onl
74.
by howerj 8y ago
I was actually interested in turning the graphics driver into something that could support CGA (like) graphics. At the moment there are no graphics modes available to the system, it's all just text. The biggest limitation is the block
75.
by howerj 8y ago
Simply because I wanted to. I prefer VHDL because that's what I was taught at university, but I don't do any HDL work professionally so don't take it as a particularly informed decision.
76.
by howerj 8y ago
I actually don't know too much about the NC4016, at a quick glance it has some similarities, especially in how the instructions are encoded. The H2 runs faster - but that's more a function of the FPGA than anything I have done. I
77.
by howerj 8y ago
The Nexys-3 board on which it runs is clocked at 100MHz, the 16-bit CPU executes a single instruction per clock cycle. I have not tried it on any new FPGAs, just on the board I have, it might run faster on a newer FPGA. It can also respond
78.
by howerj 8y ago
Hi! Author here, this has been a fun side project for me, It's pretty much finished but I keep coming back to it to do one more thing. This project is a CPU written in VHDL that executes Forth. It's based on the J1 processor, but
79.
Show HN: H2 Forth CPU(github.com)
120 points by howerj 8y ago|26 comments
80.
by howerj 8y ago
Those tricks certainly are necessary to compile Forth, it's common to define words that create new words for custom data structure, which extend the grammar of Forth. Any time you use 'create ... does>' you are in effect e
81.
by howerj 8y ago
Yes it does, in fact it is pretty much the canonical definition of something being hard to parse. Given an arbitrary Forth program you can't even tell if the parser will terminate. Granted, the non-fixed grammar starts off simple, but
82.
by howerj 8y ago
On the contrary, it requires a Turing machine to parse fully.
83.
by howerj 8y ago
Yes...and far more accurately no, you can't actually write a parser for Forth with a fixed grammar, you can only write a complete interpreter for it as it is capable of modifying its own grammar on the fly. It is possible to define new
84.
Forth SoC written in VHDL(hackaday.com)
2 points by howerj 9y ago|0 comments
85.
by howerj 10y ago
The Serious Sam engine also had this capability: https://www.youtube.com/watch?v=8bmTUgySSyk , which I thought was pretty neat. I don't have any experience with Game design, but I thought this more dynamic behavior woul
86.
by howerj 10y ago
I usually make my own dialects of languages that already exist, I got furthest making my own Forth and Lisp interpreters. As for why, the best way of learning a new language, for me at least, it to implement (or even just trying to implemen
87.
by howerj 10y ago
I've just started writing my own PL/0 compiler, I found the best resource for it (apart from the Wikipedia articles on EBNF, PL/0 and P-Code) is Wirth's book "Compiler Construction" ( http://www.ethob
88.
by howerj 10y ago
You can use your adblocker (well, uBlock origin) to block the elements that popup over the article.
89.
by howerj 10y ago
I think a lot of the larger devices do this, otherwise there would be a lot of repetition across the family.