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Hello HN, here is a project that I have recently finished, it is a very niche CPU written in VHDL and verified to work on an [FPGA][]. It is a 16-bit [bit-seri
by howerj 6y ago
Hello HN, here is a project that I have recently finished, it is a very niche
CPU written in VHDL and verified to work on an [FPGA][]. It is a 16-bit [bit-serial][]
CPU, which means the processor is incredibly slow taking 102 clock cycles to complete
some instructions, the trade-off is that the CPU is very small, almost being free to implement
in terms of floor space on the FPGA, the entire project takes just 73 slices, with the
CPU itself taking 23 slices.
The cross-compiler and the cross compiled program, a [Forth][] interpreter, are available at:
<https://github.com/howerj/bit-serial/blob/master/bit.fth https://github.com/howerj/bit-serial/blob/master/bit.fth>
It compiles down to an image that uses just 4802 bytes (out of 16KiB).
And a C simulator if you would like to try out the Forth interpreter but lack an FPGA to try
things on is available at:
<https://github.com/howerj/bit-serial/blob/master/bit.c https://github.com/howerj/bit-serial/blob/master/bit.c>
You can type:
make run
To build the C simulator and run it on a pre-compiled image. Typing 'words' and hitting
return shows you a list of all defined functions.
In all likeliness the project will not have that much utility to anyone, but I have
wanted to make a bit-serial CPU after completing my previous FPGA project because the
architecture is quite rare nowadays and might be something of a curiosity.
[bit-serial]: https://en.wikipedia.org/wiki/Bit-serial_architecture https://en.wikipedia.org/wiki/Bit-serial_architecture
[Forth]: https://en.wikipedia.org/wiki/Forth_(programming_language) https://en.wikipedia.org/wiki/Forth_(programming_language)
[FPGA]: https://en.wikipedia.org/wiki/Field-programmable_gate_array https://en.wikipedia.org/wiki/Field-programmable_gate_array
[VHDL]: https://en.wikipedia.org/wiki/VHDL https://en.wikipedia.org/wiki/VHDL
- maxmcd 6y agoIncredible, thanks for sharing
- jhallenworld 6y agoVery nice! It's too bad that FPGAs don't have serial loading address registers for the RAMs.. save even more space. BTW, there is a RISC-V bit-serial CPU (so you can use GCC): https://github.com/olofk/serv https://github.com/olofk/serv I don't know how big, but they are certainly targeting tiny FPGAs.
- zik 6y agoThis is awesome. I've often thought of doing a bit serial CPU project. Yours looks great.
- howerj 6y agoThanks! Making the initial (working) version of the CPU was fairly easy, however I wanted to do more than just write in low-level assembly and blink lights on and off, so keeping the system small whilst being able to support a higher level language like Forth actually took most of the time.
- cellularmitosis 6y agoVery cool! For those of us less versed in FPGA, do you have an idea of how many transistors would be required to build this CPU? I have long been curious about the minimum number of transistors needed to build the smallest "useful" CPU.
- howerj 6y agoI do not think I could give an accurate conversion between FPGA Slices and transistors myself, it is certainly small (23 slices) and processors with similar capabilities ran in thousands of transistors/tubes range. You should look into more esoteric processors such as Forth CPUs, other bit-serial CPUs, CPUs built around single instructions (such as SUBLEQ) and new CPUs built out of 7400 series parts.
- LargoLasskhyfv 6y agoWhile I'm currently not in the mindset to play with it, GOOD JOB! Plus for VHDL and FORTH, Github page looks good too.