hajile

41 ms·

451.
by hajile 2y ago
Anandtech shows[0] that M3 is massively ahead in integer performance, but slightly behind in float performance on Spec 2017. Integer workloads are by far the most common, but they tend to not scale to multiple cores very well. Most workload
452.
by hajile 2y ago
Unlike x86, none of this is strictly necessary. As long as you put things back as expected, you may use all the registers however you like.
453.
by hajile 2y ago
With 16 registers, you can't just avoid a register because it has a special use. Instead, you must work to efficiently schedule around that special use. Lack of special GPRs means you can rename with impunity (this will change slightly
454.
by hajile 2y ago
Determining the end of a RISC-V instruction requires checking two bits and you have the knowledge that no instruction exceeds 4 bytes or uses less than 2 bytes. x86 requires checking for a REX, REX2, VEX, EVEX, etc prefix. Then you must che
455.
by hajile 2y ago
> Getting 32% higher performance from 17% more cores implies higher performance per core. I don't disagree that it is higher perf/core. It is simply MUCH worse perf/watt because they are forced to clock so high to achieve
456.
by hajile 2y ago
I spent $1700 or so on my M1 Air not too long after they were released. A ThinkPad X1 Carbon would have cost me more money for massively worse performance. Quality costs more. The difference is that a 4800U would be looking pretty bad vs a
457.
by hajile 2y ago
Perf per watt is higher for M1 on N5 vs Zen5 on N4P, so the problems go deeper than just process. X Elite also beats AMD/Intel in perf/watt while being on the same N4P node as HX370. https://www.notebookcheck.net/A
458.
by hajile 2y ago
Laptops vastly outsell desktops, so this tradeoff means hurting the majority of your customers to please a small minority. Servers also care about perf/watt a LOT and they are the highest profit margin segment. Why would AMD choose a t
459.
by hajile 2y ago
1. The biggest chip market is laptops and getting 15% better performance for 80% more power (like we saw with X Elite recently) isn't worth doing outside the marketing win of a halo product (a big reason why almost everyone is using sl
460.
by hajile 2y ago
RISC-V has a different version of this issue that is pretty straight-forward. Preferring 2-register operations is already done to save register space. The only real extra is preferring the 8 registers C uses for math. After this, it's
461.
by hajile 2y ago
1. Why would you WANT to hit 5+GHz when the downsides of exponential power take over? High clocks aren't a feature -- they are a cope. AMD/Intel maintain I-cache and maintain a uop cache kept in sync. Using a tiny part to pre-deco
462.
by hajile 2y ago
Halo products with high scores sell chips. This isn’t a new idea. So you lower the wattage down. Now you’re at M1 Pro levels of performance with 17% more cores and nearly double the die area and barely competing with a chip 3 years older wh
463.
by hajile 2y ago
I think you may be correct about gracemont v golden cove. Rumors/insiders say that Intel has supposedly decided to kill off either the P or E-core team, so I'd guess that the P-core team is getting layed off because the E-core IPC
464.
by hajile 2y ago
You can read the notebookcheck review for yourself. https://www.notebookcheck.net/AMD-Zen-5-Strix-Point-CPU-anal...
465.
by hajile 2y ago
https://www.notebookcheck.net/AMD-Zen-5-Strix-Point-CPU-anal... They got those kinds of numbers across multiple systems. You can take it up with them I guess. I didn't even mention one of these systems was peaking at 5
466.
by hajile 2y ago
I stacked the deck in AMD's favor using a 3-year-old chip on an older node. Why is AMD using 3.6x more power than M1 to get just 32% higher performance while having 17% more cores? Why are AMD's cores nearly 2x the size despite be
467.
by hajile 2y ago
3. You can look up the papers released in the late 90s on the topic. If it was O(n log n), going bigger than 4 full decoders would be pretty easy. 6. Not all of those SIMD sets are compatible with each other. Some (eg, SSE4a) wound up casua
468.
by hajile 2y ago
https://oscarlab.github.io/papers/instrpop-systor19.pdf ARM64 instructions are 4 bytes. x86 instructions in real-world code average 4.25 bytes. ARM64 gets closer to x86 code size as it adds new instructions to replace
469.
by hajile 2y ago
Let's do the math on M1 Pro (10-core, N5, 2021) vs HX370 (12-core, N4P, 2024). Firestorm without L3 is 2.281mm2. Icestorm is 0.59mm2. M1 Pro has 8P+2E for a total of 19.428mm2 of cores included. Zen4 without L3 is 3.84mm2. Zen4c reduce
470.
by hajile 2y ago
I think there's a lot of hope for a Strix Halo mini-PC. We currently have 7840HS+6650M with two massive heatsinks just barely coming in at what you would consider a large mini-PC rather than a SFFPC. Just one chip cuts the heatsink dem
471.
by hajile 2y ago
That stuff is WAY out-of-date and was flatly wrong when it was published. A715 cut decoder size a whopping 75% by dropping the more CISC 32-bit stuff and completely eliminated the uop cache too. Losing all that decode, cache, and cache cont
472.
by hajile 2y ago
Clam makes some serious technical mistakes in that article and some info is outdated. 1. His claim that "ARM decoder is complex too" was wrong at the time (M1 being an obvious example) and has been proven more wrong since publicat
473.
by hajile 2y ago
My father-in-law died of cancer late last year. He commented that cancer was a kind disease because it allowed him the luxury of planning his last days, making peace, and saying goodbye. I wish you happiness, love, and comfort right up to t
474.
by hajile 2y ago
ARM64 threw out the book and started over. Stuff like Thumb-2 or VFPvX are for legacy ISA. There aren't variable instruction lengths and NEON is baked into the core of the ISA. AES in ARM (and x86 as this was after their attempt to be
475.
by hajile 2y ago
Look into Intel's iAPX and tell me that ISA doesn't matter. How would you go about making that pile of garbage into something fast? Most CISC designs died. A large part of x86's survival is because it wasn't exceptionall
476.
by hajile 2y ago
What about ARM64 is not RISC? RISC was not just about total instructions, but the complexity of those instructions. It's fundamental conceit is that every instruction should ideally take just one cycle to execute. Intel's iAPX432
477.
by hajile 2y ago
https://www.cs.cmu.edu/%7Erwh/papers/mtc/short.pdf I believe modular implicits and modular typeclasses are similar and aim to solve the same issues, but they are not quite the same.
478.
by hajile 2y ago
It's an interesting question. JS uses a JIT while Ocaml is AOT which is generally an advantage for Ocaml. Ocaml only compiles once while JS compiles every time it runs. This means that JS is a lot more selective about its compilation,
479.
by hajile 2y ago
I think the real answer is adding actually sound types to JS itself. One of the biggest revolutions in JS JITS was the inline cache (IC). It allows fast lookup and specialized functions (which would be too expensive otherwise). These in tur
480.
by hajile 2y ago
Ocaml messed up with their operators. StandardML had a better approach and I hope a future version adds module typeclasses (to help limit the type soup we see in Haskell). As I wrote elsewhere in this thread, TS makes it incredibly easy to

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