hadibrais

5 ms·

1.
The Intel x86 Microarchitectures Map [pdf](hadibrais.files.wordpress.com)
2 points by hadibrais 6y ago|1 comments
2.
by hadibrais 6y ago
From the blog post at: https://hadibrais.wordpress.com/2020/04/02/the-intel-x86-mic...
3.
The Linux Perf Event Scheduling Algorithm(hadibrais.wordpress.com)
1 points by hadibrais 7y ago|0 comments
4.
by hadibrais 7y ago
There are many (small) differences between AMD64 and Intel 64. But it's obvious that the Intel processor implements the Intel 64 version of x64 and the AMD processor implements the AMD64 version. This also goes for VT-x, VT-d, and AMD-
5.
by hadibrais 7y ago
They should specify what benchmarks and input sets were used and the benchmarking methodology. It'd be nice to also see the standard deviation plotted on these bars.
6.
by hadibrais 7y ago
Not yet. In the meanwhile, you can instead use the latest version of AMD μProf ( https://developer.amd.com/amd-uprof/ ), which does support Zen 2.
7.
Considering Snoops When Counting Cache Hit and Miss Events on Client Processors(hadibrais.wordpress.com)
2 points by hadibrais 7y ago|0 comments
8.
Understanding the Cache Hit and Miss Performance Monitoring Events(hadibrais.wordpress.com)
1 points by hadibrais 8y ago|0 comments
9.
The Significance of the x86 Sfence Instruction(hadibrais.wordpress.com)
1 points by hadibrais 8y ago|0 comments
10.
The Significance of the X86 LFENCE Instruction(hadibrais.wordpress.com)
3 points by hadibrais 8y ago|0 comments
11.
by hadibrais 8y ago
I don't much about Java. But, for example, if you want to implement the technique from the link above in Java, you'd need LoadFloat8, BroadcastFloat8, and AdduFloat8. I'm not sure how they are implemented in Glow, but they ca
12.
by hadibrais 8y ago
Sparse matrix multiplication is generally considered to be a different problem. Sparse matrices need to be represented differently (See https://en.wikipedia.org/wiki/Sparse_matrix for an introduction). There has been r