dspwizard

5 ms·

1.
by dspwizard 2mo ago
I wish I could upvote this twice !
2.
by dspwizard 2mo ago
It is really puzzling how a GPU could work in such latency constrained environment like RU. On the cost side - RU are built with on chip SRAM as a processing memory for cost,latency and power reasons, which is completely opposite of how GPU
3.
by dspwizard 8mo ago
VLIW works great when you have predictable & short latencies of memory accesses - you will not find DSP designs that do not use TCM (core local SRAM). So you program DMAs input data into its own TCM and work on it from there. GPUs on th
4.
by dspwizard 8mo ago
TI C2000 is one example
5.
by dspwizard 8mo ago
Cadence DSPs have C++17 compatible compiler and will be c++20 soon, new CEVA cores also (both are are clang based). TI C7x is still C++14 (C6000 is ancient core, yet still got c++14 support as you mentioned). AFIR Cadence ASIP generator wil
6.
by dspwizard 2y ago
Most of VRAN sites will be still DRAN (distributed RAN -server on site). CRAN (centralized RAN) is a fairy tale so far and works very few scenarios like very dense urban. Still we are talking about 200/400G NICs being standard. L1 inte
7.
by dspwizard 7y ago
The most amusing part is that Huawei developed 5G tech on its own - nokia has shit and e/// is not better. Even in regards of 4G massive MIMO tech - Huawei is years ahead of other, they couldn't steal this tech from anyo
8.
by dspwizard 8y ago
Huawei is far ahead of others in mMIMO technology and have this implemented in their BTS boards, although right now it is done in FPGA not ASIC.
9.
by dspwizard 8y ago
I had to register to comment about TI "quality" and friendliness ;-). Their SoCs are ridden with HW bugs and TI will not put every HW bug to errata - e.g. their infrastructure pktdma will hang if you will use chained descriptors b