domipheus

5 ms·

1.
by domipheus 11y ago
This is some great stuff, thanks for all the feedback - seriously. My VHDL experience is probably about 2/3 online tutorials, and they were all behavioural. The main aim of the articles are for me to learn. The point about documentatio
2.
by domipheus 11y ago
Hah, don't worry - I didn't think it was harsh. I've had no training/edu in HDL whatsoever, so this was a deep dive - I expected to be told I'm doing wrong! The end result is on FPGA, yes. Still a long way before th
3.
by domipheus 11y ago
Hey - author here. I'm not wanting to learn industry practices, it's a hobby project. May look into things like that later, though. The other article parts have the disclaimer that says I have no idea what I'm doing ;) Cheers
4.
Designing a CPU in VHDL, Part 3: Instruction Set Architecture, Decoder, RAM(labs.domipheus.com)
2 points by domipheus 11y ago|0 comments
5.
by domipheus 11y ago
Thanks for the advice! I've been synthesizing a bit, fixing a few issues that at least didnt present when building for the simulator. I've yet to run it actually on hardware, though - that part will be fun. Webpack does still come
6.
by domipheus 11y ago
Cheers for the tips. I'll eventually move to Verilog, but as others point out, I think it's good to walk before I run. Regarding pipelining, I'm getting right on it - and the iterative benchmarking is something I plan to do.
7.
by domipheus 11y ago
yes! I've not implemented conditional jump to an immediate offset yet, so you need the branch target in a register.
8.
Teensy Z80 Computer – Part 4 – VRAM explained, display modes, simple shell(labs.domipheus.com)
3 points by domipheus 12y ago|0 comments
9.
by domipheus 12y ago
Hey folks, writer here. Thanks for the great comments! Part 2 is already up talking interrupts (same blog) and i'll be cheating even more when the SD card interface comes online.