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djf
searching PlanetScale…
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by
djf
17y ago
After a think, ignoring the VHDL syntax,I think the Verilog example has edge sensitive set/reset, whereas the VHDL has level sensitive set/reset? I don't write Verilog mind so I'm guessing a bit...
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by
djf
17y ago
Assuming the second one is supposed to be VHDL, there are so many syntax errors that I can't figure out what the OP's intent is...