dfox

29 ms·

361.
by dfox 3y ago
The idea is that in typical assymetric cryptosystem you do some variant of bitwise exponentation of “large values” (ie. slow) and both the power envelope and timing is directly related to individual bit values of the private key. This trivi
362.
by dfox 3y ago
LCD TVs and even computer displays are somewhat notorious for dodgy power supply designs. I assume that it is because CRT TVs and displays were essentially an one giant SMPS and that reasoning was reused for later LCD based designs.
363.
by dfox 3y ago
It is big enough that it makes sense to run some kind of small RTOS on it, especially given the dual core nature of the thing.
364.
by dfox 3y ago
The point is that the CA has no way to determine that the CSR was generated by Qualified Device and will just sign it. My view of all the talk about Qualified Devices in eIDAS exists mostly to force QCAs to use normal enrollment process wit
365.
by dfox 3y ago
> It's disaster when system handling user data is showing data for another user and this is how I understand effects of https://curl.se/docs/CVE-2023-27536.html manifesting in real world. It was wrong even befo
366.
by dfox 3y ago
AdES is mostly an technical standard that specifies how to use existing PKCS and IETF standards to produce eIDAS conforming signature, timestamp or “seal” (ie. timestamped signature) and how that should be mapped onto CMS (CAdES), XML-Signa
367.
by dfox 3y ago
The service probably has nothing to do with email and is only tangentially related to eIDAS. At least that is the case in Czech Republic. One surprising fact about such systems is that they tend to produce blockchain-like audit log and pred
368.
by dfox 3y ago
This touches on a issue that is a part of how we got to this situation. What is the encoding of zero and possibly slash delimited blobs of bytes (filenames, argv, envp…) that you get from and pass to the kernel? There are parts of userspace
369.
by dfox 3y ago
Method that is declared as only ever returning bool can also raise any exception that is an instance of java.lang.RuntimeException (which includes NullPointerException) this somewhat bizzare design which combines unchecked and checked excep
370.
by dfox 3y ago
I think that the only thing that prevents you from ignoring the memory controller and initializing the rest of x86 board while still remaining in the CAR mode is the sheer ridiculousness of doing that. As for whether you have an memory-mapp
371.
by dfox 3y ago
> it was a viable alternative to Windows Explorer Because there was no "Windows Explorer" before Windows 95 and the "MSDOS Executive"/"File Manager" that was used before that was truly horrible and non
372.
by dfox 3y ago
Because different colors usually mean different semiconductor material and thus different forward voltage of the junction which in practical terms leads to different brightness if the same resistor value is used.
373.
by dfox 3y ago
Wistron is large part of the reason why IBM/Lenovo ThinkPads are regarded as some kind of etalon of quality and repairability. I assume that most of the issue there is misunderstanding of how to run a factory in India and how is that d
374.
by dfox 3y ago
Because not caring how FP values are stored and what the implications are (or even not realising that you favorite programming language uses FP by default) is a particularly fast way to become the "minus 10 times programmer". Stor
375.
by dfox 3y ago
AM4 has 12 dedicated GPIO pins and ~30 pins where GPIO is shared with other functions. On the other hand these are mostly meant for platform control, and maybe blinking LEDs, not for user-space bitbanging something there. Also of note is th
376.
by dfox 3y ago
It seems that the binary in question just writes the logfile directly and does not use syslog.
377.
by dfox 3y ago
One thing that this article mentions is that MIDI is a interface that is inherently optically coupled. The notionally differential wires end up in the LED inside of an optocoupler. Reason for that design is a general aversion of audio peopl
378.
by dfox 3y ago
The idea there is that on i386 doing memory copy by explicit optimized assembly loop is faster than using CPU instruction that does that. And then there are i386 implementations that can do that faster (eg. 80386 itself) that are deprecated
379.
by dfox 3y ago
The authentication model is based on Radius with EAP, the main point is that anything after and including 3G does mutual authentication and in 4G/5G this is based on IETF protocols, in theory, you can associate with 4G network with wha
380.
by dfox 3y ago
ARM is a weird beast across the spectrum of RISC designs. The original ISA design is inspired by Berkley RISC (which had only two stage pipeline) and then optimized to what can be reasonably cheaply done in the silicon process used, with th
381.
by dfox 3y ago
Connector where both of the mating parts are the same. See the linked IBM's data connector for the probably most common historical example (incidentally it is not specific to Token Ring, but part of IBM's structural cabling system
382.
by dfox 3y ago
That is because SKILL is really an scheme under the hood. And somebody had the bright idea of making the syntax more "user friendly" (read: more like C) by inventing a rule that "foo(bar)" parses as "(foo bar)"
383.
by dfox 3y ago
ST80 does not really do the object controlled message dispatch that was there in earlier Smalltalks. Well, you can override Behavior>>#doesNotUnderstand: and do all sorts of cool tricks with that, but it is mostly meant as error-recov
384.
by dfox 3y ago
Typical Linux installation will not rely on TPM in any way. But if you use systemd-cryptenroll to provide BitLocker-like UX for FDE then the concerns are mostly same.
385.
by dfox 3y ago
The instructions that took advantage of FPM DRAM already existed in ARM1, only the implementation was different. And exactly these instructions (that essentially do the RISC/SPARC-like register window shift as an explicit operation) ar
386.
by dfox 3y ago
The point there is that for the “traditional” RISC pipeline you need to read 32b worth of instruction from somewhere every cycle. You cannot do that if the only thing you have is one 32b wide bus to the outside world. First ARMs solved this
387.
by dfox 3y ago
One notable point in there is that the thing that everyone things of when you say “RISC pipeline” (ie. MIPS) simply has to have an I-cache, because without it you simply do not have the memory bandwidth to do anything other than reading ins
388.
by dfox 3y ago
486 vs ARM is a good comparison as both are the extreme cases of CISC and RISC designs. So much that for a real instruction mix generated by reasonably modern compilers (think gcc3 and up), 486 is actually more of an RISC than ARM with its
389.
by dfox 3y ago
Another thing that was somewhat relevant at the time was ability to do arithmetic directly on tagged fixnum values. For example SPARC includes (somewhat unusable unless you write the Lisp implementation as a whole OS) instructions for that.
390.
by dfox 3y ago
I suspect that this truly bizarre design was motivated by how the Sun-provided SunRay firmware could be extended without rewriting the thing outright (and running ALP client as an userspace process on a real OS as was done in later SunRay l

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