The point there is that for the “traditional” RISC pipeline you need to read 32b worth of instruction from somewhere every cycle. You cannot do that if the only

The point there is that for the “traditional” RISC pipeline you need to read 32b worth of instruction from somewhere every cycle. You cannot do that if the only thing you have is one 32b wide bus to the outside world. First ARMs solved this by somewhat complex sequencer and not that deep pipelining. Another thing is that anything off-chip is going to be at least two clock cycles as you do not want the however fast off-chip memory to be part of your critical path. But well, many RISC designs had off-chip SRAM caches, sometimes even ridiculously large (PA-RISC is a prime example).