crest

16 ms·

241.
by crest 2y ago
You could argue that it was an oversight by Raspberry Pi to default to the cores without TrustZone if the configuration read from OTP was invalid. It doesn't matter that those cores are RISC-V an ARM -v6M or -v7M core would've wor
242.
by crest 2y ago
The problem is that this isn't an attack against a single chips unique code signing key, but against all RP2350 ever produced with this hardware revision. The problem can't be fixed in software. Now the attack doesn't require
243.
by crest 2y ago
The RISC-V cores are innocent accomplices. Having a mix of cores with and without secure boot gives attackers more tool to play with. The exploit works because if both sets of cores are "permanently" disabled the hardware state ma
244.
by crest 2y ago
Afaik the internal pull-up/-down resistors aren't strong enough to stay outside of the problematic input voltage range and external ≤ 8kΩ resistors to 3.3V aren't acceptable unless you don't care about power consumption
245.
by crest 2y ago
It was a cool talk. The attacker used a well timed glitch on voltage supply pin shared by the USB peripheral and OTP (one time programable) memory which unlike the CPU power isn't protected by hardware glitch detectors. Instead the Boo
246.
by crest 2y ago
Oh there is an obviously correct way to do it: have two radios able to switch channels with without impacting traffic, but that costs more money as well as space and power. No lets just retrofit this crap into existing drivers and hope nobo
247.
by crest 2y ago
The authorisation prompt doesn't show up once you denied. Which makes sense to avoid user fatigue, but is annoying when users denied it the first time (aka "go away stupid modal dialog") and now complain about things working
248.
by crest 2y ago
So the issue is that the frontend which "eliminates" those operations doesn't make the resulting values available to the backend if fits Intel's ad-hoc definition of a short immediate (which shift values do) and since th
249.
by crest 2y ago
Depends on your colour palette :-P.
250.
by crest 2y ago
In what way(s) do you consider the Dreamcast hardware vastly superior? It had a slower CPU, slower GPU, and less memory if I remember correctly.
251.
by crest 2y ago
Apple shouldn't be allowed to lock down APIs between system components to give themselves a competitive advantage, but that doesn't mean Meta should be allowed decide if they're getting that access. Let Apple offer users the
252.
by crest 2y ago
There're more options, but those require multiple nation states to work together in a conspiracy (everyone in the know) and all others to be incompetent. Given just publicly known facts and Occam's razor…
253.
by crest 2y ago
That's because if this theory is correct from the point of view of the SSD there was no reboot yet, because there was never any total power loss.
254.
by crest 2y ago
Only if you care about about causation instead of just correlation.
255.
by crest 2y ago
The sound of silence can be deafening.
256.
by crest 2y ago
Is there a version with a three (or even four) port VLAN capable switch? One port for the BMC, one looped back into the normal NIC and one (or two) upstream ports? Of course it would require a full height PCI bracket, but it would be perfec
257.
by crest 2y ago
They haven't gone with a 64Bit ARM core. The ARMv8*M* isn't 64bit unlike ARMv8R and ARMv8A (the nomenclature can get confusing). The differences between ARMv7M (especially with the optional DSP and FPU extension) and ARMv8M mainli
258.
by crest 2y ago
Will open-source developers unable or unwilling to sign an NDA get access to a toolchain to run their own code on the RISC-V co-processors? Is the bus matrix documented somewhere? Does the fast co-processor have access to DMA engines and in
259.
by crest 2y ago
They would have to fuck up massively for an I/O co-processor to lack single cycle GPIO access which would at least allow driving a 320/2 50% duty-cycle square wave, but sustaining that deterministically through priority access to
260.
by crest 2y ago
The Radeon VII is special compared to most older (and current) affordable GPUs in that it used HBM giving it memory bandwidth comparable to modern cards ~1TB/s and has reasonable FP64 (1:4) throughput instead of (1:64). So this card ca
261.
by crest 2y ago
One the one hand adding radios (WiFi, LTe) to KVM over IP device sounds tempting on the other hand given the track record of KVM over IP devices it sound terrifying to give them the ability of bypass points of policy enforcement.
262.
by crest 2y ago
The CCC is a big believer in self hosting there is a live streaming platform during the event and media.ccc.de afterwards.
263.
by crest 2y ago
There is a realtime translation team that's available as an audio track in the life streams as. The translation is done be volunteers. The last ~5 years they managed to translate all the German and English slots on the official stages.
264.
by crest 2y ago
It's an option for those on a tight budget aka "beggars can't be choosers". Hotels are a lot cheaper if you book a (fully) refundable stay months in advance instead of waiting until you have a ticket.
265.
by crest 2y ago
All of these didn't just give you something equivalent to C malloc()/free() with a parameter and result type. Maybe monads are useful in a lot of cases, but require a safe type system that prevents accidentally/negligently ig
266.
by crest 2y ago
The answer is to make enums explicit e.g. malloc should return either a valid allocation or an error, but you can't easily do that in C. It takes a richer/better type system to make this convenient to use and safe from accidents.
267.
by crest 2y ago
Well the RP2040 has a QSPI controller but it has only a single channel that is normally the "boot device". If you bootstrap via SWD (or USB) this device could be at least a QSPI RAM, but writes would have to trapped and implemente
268.
by crest 2y ago
The RP2040 has a single QSPI controller channel, but with clever hacks you can multiplex that to boot from SPI and switch over to some other (Q)SPI peripheral, but iirc you can't write directly (can be emulated via MPU+DMA). What'
269.
by crest 2y ago
Even those implement communication primitives e.g. locks, semaphores, mailboxes, etc. as part of the OS. Some of the larger ones also define a driver model of sorts (which often just codifies the structure of the first driver for that type
270.
by crest 2y ago
You can run uC Linux without an MMU, but you won't get memory safety. Better microcontrollers (that includes the RP2040 and RP2350) have an MPU (memory protection unit) to implement memory safety, but almost no microcontroller has a re

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