crest

33 ms·

541.
by crest 3y ago
The PRUs are simple single-issue in-order CPUs designed to make cycle-counting easy. They are more than an accidentally turing complete useful combination of a down-counter and shift-register. Don't get me wrong the RP2040 PIO is a ver
542.
by crest 3y ago
The emulator doesn't pass through right clicks and the mouse wheel.
543.
by crest 3y ago
The old "pixel art" UI and fonts could fit a lot more on low resolution screens, but there is no reason we should use them on modern >200PPI displays. The real "crime" of modern UI/UX are undiscoverable low contr
544.
by crest 3y ago
I use it as my default file system on FreeBSD. It was rough in FreeBSD 7.x (around 2009), but starting with FreeBSD 8.x it has been rock solid to this day. The only gotcha (which the documentation warns about) has been that automatic block
545.
by crest 3y ago
"Telemetry" above everything.
546.
by crest 3y ago
I'm sure it will produce innovative business practices inflicted on a captive userbase.
547.
by crest 3y ago
The solution is to avoid synchronous blocking operation like migrating cache lines more often than required. An other solution is to offer a batch produce()/consume() API to process multiple elements per invocation. A double mapped rin
548.
by crest 3y ago
If it's a power of two you can use a longer than required index. An empty buffer will have all index bits equal. A full buffer will have the higher bits different but the lower bits equal. This requires extracting only the lower bits f
549.
by crest 3y ago
VIPT caches only allow this if all virtual aliases for the physical memory backing them map to the same cache set. Let's look at an example: Writing to the first cache line in both aliases of such a double mapped ring buffer. The data
550.
by crest 3y ago
It is a cool trick and even without virtual memory if the maximum read size has a low upper bound just copying a the first few bytes from the beginning to the end can be worth it to avoid the complexity and overhead of indexing into the rin
551.
by crest 3y ago
Didn't some of the DEC Alpha and IBM Power designs use a cached register-file for lack of a better terminology. Allowing them to support more architectural state than the wide multi-ported register file could fit? Would a small double&
552.
by crest 3y ago
TLS isn't worth much if someone hijacks your zone and obtains X.509 certificates for your services. A smart attacker with enough resources could even re-encrypt the intercepted traffic and control enough addresses to avoid running into
553.
by crest 3y ago
The cheeky answer would be to throw away the trash every decade, but the real answer is that there is tooling in place to pick the best possible implementation of a function at link time on modern *nix systems to target several levels of SI
554.
by crest 3y ago
Run `/ipv6/settings/export verbose` to show you the combination of your configuration and the default values on the relevant subtree. I would've expected the `disable-ipv6` to disable all ICMPv6 processing including the
555.
by crest 3y ago
Good luck finding a lawyer without an optical drive to take your case :-P-
556.
by crest 3y ago
It's easier and cleaner to automate than sending SSH commands.
557.
by crest 3y ago
What's wrong with SSH and API access?
558.
by crest 3y ago
The report says it can be exploited with IPv6 enabled, but IPv6 forwarding disabled and reception of router advertisements conditional on the this aka stop looking at router advertisements if the system is configured as IPv6 router.
559.
by crest 3y ago
The M1 uses 16kiB pages to reduce TLB pressure and get more non-aliasing cache tag bits.
560.
by crest 3y ago
Sometimes you have to lead them by the neck. Wipe out the company and lock up those responsible for a few decades of real labor.
561.
by crest 3y ago
A 1% error rates for corrupting other blocks is prohibitively. A file system would have do extensive forward error correction in addition to checksumming to have a chance to work with this. It would also have to perform a lot of background
562.
by crest 3y ago
A state is also a threat to its citizens. It's power must be limited through careful checks and balances. These create intentional inefficiencies. Combining the internal policing function with external espionage creates an organisation
563.
by crest 3y ago
A lot of times mathematical notation use domain specific naming conventions for they variables and each the tradition is a leftover from a time when you had to write the whole line (by hand) for every step you wrote down and only a few name
564.
by crest 3y ago
So is using binary packers like UPX. Not just will they sound the alarm in a lot of so called security products, but they'll also prevent the operating system from sharing the RAM used to mmap() read-only and read-execute pages from th
565.
by crest 3y ago
Does this mean we're finally closer to getting CoreBoot on Intel consumer boards from this decade, because everyone can sign a valid image?
566.
by crest 3y ago
They still have to compute the Ethernet frame check sequence.
567.
by crest 3y ago
I guess it depends on how long the batch jobs run and how much they impact interactive use compared to the normal dayshift workload.
568.
by crest 3y ago
Recentish macOS versions include 464XLAT as well, but it isn't enabled on WiFi and Ethernet (by default).
569.
by crest 3y ago
That's the official spec, but given how far the rest of the chip overclocks i would like to check that. The problem is that non of my SWD probes go above 24MHz.
570.
by crest 3y ago
The original Cray 1 had already had a very powerful vector execution unit and low memory latency relative to the CPU frequency (by todays standards). The RP2040 has even lower memory latency, but only ¼ MiB RAM and no hardware floating poi

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