The original Cray 1 had already had a very powerful vector execution unit and low memory latency relative to the CPU frequency (by todays standards). The RP204

The original Cray 1 had already had a very powerful vector execution unit and low memory latency relative to the CPU frequency (by todays standards). The RP2040 has even lower memory latency, but only ¼ MiB RAM and no hardware floating point support or SIMD (neither packed-SIMD nor "true" Cray style vectors). At least the BootROM includes hand optimised Soft-FP code and the single-cycle I/O block even includes a memory mapped hardware integer divider and two interpolators per CPU core. These can help a lot with fixed point DSP workloads, but are totally different from what made the Cray 1 special at its time. Todays better MCUs may match certain performance numbers of early supercomputers, but their designs have more differences than similarities. There have been attempts to recreate early Crays in FPGAs, but so little software for them has been preserved (in a way accessible to the public) that it's difficult to judge how good the recreations are and even the later Cray 1 based designs need a really big FPGA to reimplement all relevant pieces at least as fast as the original. Cray didn't just build fast floating point adders and multipliers, but the main memories and interconnects between them to make them useful. Good luck finding a way to attach 100s of interleaved DRAM banks to your FPGA, because your internal block RAM won't be enough as main memory and memory access timings have improved the least over time.