brigade

29 ms·

331.
by brigade 5y ago
Bandwidth yes, latency no. Wiring out 32 channels of DDR5 to 16 slots might not be feasible, but latency-wise Anandtech's measurements suggest the M1 Max actually has a bit higher latency to memory than e.g. Icelake-SP
332.
by brigade 5y ago
It is clocked 1.6x higher than M1 chips (single-core), but also the CPU architecture isn't from 2015 like Intel's desktop chips were from generation 6 through 10. A single core at that 5.2GHz turbo can consume ~40W alone, however.
333.
by brigade 5y ago
100W of that is probably for the USB ports; afaik TB4 ports are required to support 15W, and I don’t think there’s been a Mac didn’t support full power simultaneously across all ports. (if that’s even allowed?)
334.
by brigade 5y ago
It's more akin to how on Intel, each core's L2 has some maximum bandwidth to LLC, and can't individually saturate the total bandwidth available on the ring bus. But Intel doesn't have the LLC <-> RAM bandwidth for
335.
by brigade 5y ago
Does Geekbench actually attempt to simulate that in their multi-core score? And how? I was under the impression that all of their multi-core tests were "run N independent copies of the single-threaded test", just like SPECrate doe
336.
by brigade 5y ago
No, there is with DSC. 144Hz with HDR, or 180Hz with SDR. Or even 240Hz with two HBR2 streams.
337.
by brigade 5y ago
There are bidirectional DisplayPort <-> USB-C cables, as well as DisplayPort+USB-A -> USB-C cables/adapters that work with the XDR display at 6k, or there are PCIe cards that add a USB-C port with DisplayPort alt-mode support
338.
by brigade 5y ago
Out of curiosity, what in ARMv9 are you looking for that isn't either optional or already mandated in ARMv8.5? I'm actually not sure what ARMv9 additionally mandates over ARMv8.5... SVE/SVE2 is optional in ARMv9 [1], despite
339.
by brigade 5y ago
How exactly do you return a null object by value? I know about RVO, but that's irrelevant here because a factory function returning an object by value does nothing to avoid needing to throw exceptions if construction fails.
340.
by brigade 5y ago
Then you can't allocate the object in-place (e.g. on the stack), and also you have to ban copy assignment/construction. Probably a more common solution is like what STL's own fstream does - don't throw an exception on co
341.
by brigade 5y ago
So if SSDs rely solely on capacitors for data integrity and lie about flushes, what do they do on a flush that takes any amount of time? Are they just taking a speed hit for funsies? Heck, from this test, the magnitude of the speed hit is
342.
by brigade 5y ago
It is part of the High 4:4:4 Predictive profile, but you can use it with 4:2:0 subsampling if you want. It's more accurate that the all profiles H.264 defined kinda sucked except for Main, and no one really thought 10bit, 422 or especi
343.
by brigade 5y ago
It's pretty typical for cops not to bother to pursue animal cruelty charges, especially if it's "just" a neighbor's pet. Then if there's any potential "defense", like the pet entering their property,
344.
by brigade 5y ago
All of those companies except Amazon have shipped ARM CPU cores fully designed in-house, yes. But all except Apple and NVIDIA have since completely dropped their custom core design, and NVIDIA goes back and forth. Qualcomm did buy Nuvia tho
345.
by brigade 5y ago
You mean Intel - older Thunderbolt displays don't support USB-C alt-mode because Intel didn't support it as input until Titan Ridge Thunderbolt controllers.
346.
by brigade 5y ago
The "serious advances" is DSC, which the XDR is already using to support 6k over a single DisplayPort HBR2 link. Which, as others mentioned, can be carried via USB-C alt-mode in addition to Thunderbolt. 6k 120Hz and 5k 144Hz are b
347.
by brigade 5y ago
More precisely, "Messages in iCloud" is orthogonal to "iCloud Backup". If you only enable "Messages in iCloud" but disable "iCloud Backup" then according to that the messages will be stored in the clo
348.
by brigade 5y ago
Yeah, this sort of conversion is pretty common for the core of arithmetic/range decoders, and I definitely don't expect a compiler to be capable of the sort of transformations needed to convert the branchy form to branchless. Thou
349.
by brigade 5y ago
It's replacing rc_bit not rc_direct (rc_direct is a fixed .5 probability), which just uses rc_bit_last, so original code is: #define rc_bit_last(prob, action0, action1, seq) \ do { \ rc_if_0(prob, seq) { \ rc_updat
350.
by brigade 5y ago
gcc and clang see the use of ternaries as a hint that they should use cmov, but it's obviously not guaranteed.
351.
by brigade 5y ago
X86 does not require any explicit barrier if you modify through the same virtual address as execution, so no.
352.
by brigade 5y ago
The JIT'd ARM code pages are W^X, and that's not optional on macOS ARM. But W^X was opt-in on x86 macOS, so for backwards compatibility Rosetta can't require the x86 code to implement it in order to function. So your model of
353.
by brigade 5y ago
Similar way register movs can have zero latency - the output is renamed from the register source of the corresponding store. Which takes the load out of the dependency chain, effectively having zero latency so long as the correct store was
354.
by brigade 5y ago
It gets more "free" once you have the zero-latency loads introduced in Zen 2 and the load can be speculatively replaced with a register move if the store is close and obvious enough
355.
by brigade 5y ago
Any H.264 decoder that doesn’t produce bit identical output is non-conformant to the spec; this was one of the big lessons of MPEG4 part 2, that you really don’t want the drift that comes from repeatedly using “near enough” reconstruction a
356.
by brigade 5y ago
On the other hand, because they're sponsored by car insurance companies, they only care about injuries from impacts. Like how them changing their whiplash tests caused neck pain and injuries for anyone significantly outside their tes
357.
by brigade 5y ago
They're both GA104, but the desktop version does have 15% more cores enabled and 30% higher clocks.
358.
by brigade 5y ago
I would be annoyed if 10% of my development time was consistently wasted because no one cares about building a foundation that doesn’t shift like quicksand.
359.
by brigade 5y ago
They’re almost certainly 20gbps TB3 cables if they have sufficient signal integrity to be in spec. Anyway, the 2m 40gbps cables I have are actually thinner, lighter, and more flexible than either of the 2m 5-10 gbps USB-C cables I have, or
360.
by brigade 5y ago
Begins? Where do SVE2's histogram instructions fit? Or even NEON's VLD3/VLD4, dating to armv7? (which can decode into over two dozen µops, depending on CPU) RISC has been definitively dead since Dennard scaling ran out; com

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