azonenberg

8 ms·

31.
by azonenberg 2y ago
I have a H735 on a retired board slated for decap so we'll find out once I open it up. Do you know if it's fabbed in house, TSMC, or Samsung? I've seen ST silicon from all 3 foundries but the only thing I've seen stated
32.
by azonenberg 2y ago
I have encountered issues with QSPI (mostly caused by the annoying prefetch queue) which is why I am switching to the FMC for FPGA interfacing (i.e. not using OCTOSPI). That was the whole point of this experiment, validating FMC as a replac
33.
by azonenberg 2y ago
Multech (multech-pcb.com) is my preferred manufacturer these days for high end stuff. I've done six layer HDI any-layer via stackups, ten layers with filled via-in-pad, RO4350B, TU872SLK, flex, 75 micron trace/space, etc. And that
34.
by azonenberg 2y ago
S1000-2 is quite cheap and lossy (Df 0.016), slightly better than Isola 370HR (0.021) but nowhere near the stuff I usually use. At my usual Chinese board house it's one of the lowest cost substrates available for prototypes since it&#x
35.
by azonenberg 2y ago
H735 is one of the single core SKUs. Just a 550 MHz M7. Would not surprise me if the M4 was there and fused off (i.e. same die as multicore H7 offerings), but it's not active.
36.
by azonenberg 2y ago
The projects in question include things like a 48 port gigabit Ethernet switch with packet datapath in the FPGA, and dual 10/25G SFP28 uplinks. You're not doing that on a MCU. Also higher end oscilloscope work (e.g. 10 Gsps 12-bit
37.
by azonenberg 2y ago
The intent is for the high performance datapath to live entirely in FPGA (and the project you're probably thinking of is switching, not routing). The MCU is for control plane only. Several hundred Mbps between the control and data pla
38.
by azonenberg 5y ago
I had some ideas for quotas but never got to the point of fully building that part of the system.
39.
by azonenberg 5y ago
The CPU used in the thesis is a barrel processor. There is a forcible context switch every clock cycle, equal priority round robin for now although more sophisticated prioritization schemes could be used. The advantage of a barrel scheduler
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by azonenberg 5y ago
I was targeting industrial control systems, medical implants, and other critical applications. So a lot of the constraints of desktop/mobile/server computing just don't apply. The assumption was that you'd end up with so
41.
by azonenberg 5y ago
This architecture also borrowed a lot from the exokernel philosophy, which would actually have provided significant speedups by cutting unnecessary bloat and abstraction. My conjecture was that this would make up for most of the overhead, b
42.
by azonenberg 5y ago
This is a SoC, addresses of on chip devices are fixed when the silicon is made. The source address is added to a packet by the on-chip router as it's received. You can send anything you want into a port, but you can't make it seem
43.
by azonenberg 5y ago
My guiding design principle was to take a trendline from monolithic kernels to microkernels, then keep on going until you had no kernel left.
44.
by azonenberg 5y ago
My long term plan was actually to do a full formal verification of the CPU against the ISA spec and prove no state leakage between thread contexts, but I didn't have time to do that before I graduated I deliberately went with a very si
45.
by azonenberg 5y ago
Keep the hardware design as simple as possible, formally verify everything critical, then run the rest as userspace software and hope you got all the critical bugs. The point wasn't to move everything into silicon, it was to move just
46.
by azonenberg 5y ago
That was the point of the research: throw away how everything has been done and explore what a clean slate redesign would look like if we had the benefit of 30-40 years of hindsight. The easiest way to implement transparent paging would be
47.
by azonenberg 5y ago
Which is why the interconnect fabric adds the source address based on who made the request. Even hardware IP blocks don't have the ability to send packets from arbitrary addresses. You can send to anywhere you want, but you can&#x2
48.
by azonenberg 5y ago
NoC addresses are implicitly part of the handle. So for example, a pointer isn't just physical address 0x41414141. The full capability is "physical address 0x41414141 being accessed by hardware thread 3 of CPU 0x8000" because
49.
by azonenberg 11y ago
We tried to record a few lectures but had technical difficulties with audio quality, they were totally garbage so they didn't get posted. To my knowledge this is the only course of its kind that has ever been taught, I had to write all
50.
by azonenberg 11y ago
You got U4, J3, P2, U2 right. U5 was a ROT13(SCTN) but your answer is close enough to get credit. U13 was a ROT13(SGQV HFO pbagebyyre), you can tell since it connects to J2. I don't recall what U1 is but you can ask marshallh (retroact
51.
by azonenberg 12y ago
> The article that the author cites the possibility of the "Secure Enclave code being able to read the UID key"; as comex mentioned yesterday [1], this isn't true. We don't know that, we just know Apple says it'
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by azonenberg 12y ago
Exactly. I wrote it to set the record straight: Apple's crypto is intended to guard against a limited class of attacks, and "the KGB is after me" is not one of them.
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by azonenberg 12y ago
If the key is kept across a battery replacement or repair procedure, then it's going to be hard-wired/fused into the chip. SRAM needs to be powered constantly to retain data. Credit cards/smartcards include self-destructs tha
54.
by azonenberg 12y ago
Disk encryption will only stop a targeted attack (someone physically gets their hands on your phone) anyway. All this does is raise the cost by a bit.
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by azonenberg 12y ago
You're assuming I'm not affiliated with siliconpr0n. I'm actually one of the main contributors to the site and took a lot of the photos on it, just not that particular one. John (my friend who actually admins the server) is f
56.
by azonenberg 13y ago
See my lecture notes: http://security.cs.rpi.edu/courses/hwre-spring2014/Lecture9_...
57.
by azonenberg 13y ago
> It's doubtful you'd have a functional chip I have a couple of fully functional examples on my desk that say otherwise. If you actually want to keep the device usable to the point that you can still solder it to a board, then