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I have encountered issues with QSPI (mostly caused by the annoying prefetch queue) which is why I am switching to the FMC for FPGA interfacing (i.e. not using O
by azonenberg 2y ago
I have encountered issues with QSPI (mostly caused by the annoying prefetch queue) which is why I am switching to the FMC for FPGA interfacing (i.e. not using OCTOSPI). That was the whole point of this experiment, validating FMC as a replacement for my legacy OCTOSPI based MCU-APB bridge. I have a previous board using QSPI reliably in indirect mode (i.e. not memory mapped) but found it was full of pain when memory mapped specifically in writes. So that firmware memory maps it for reads but switches to indirect mode for writes. And has cache disabled.
So far I have it working quite reliably (my test firmware does a loopback test with 100K reads/writes of a 32-bit register at the start that I had written with intent of using it for link training of the PLLs to optimize read/write capture timing but never ended up using as such) and my iperf test can push tens of thousands of packets per second without issue.
- 15155 2y agoThe NXP IMXRT-series chips have a similar EMC (external memory controller) as well as "FlexIO" - PIO-like programmable IO. I've used both for this kind of FPGA interface without issue. The IMXRT1064 is around $7 and is also an M7 core with an HS USB PHY, programmable PLL-connected LVDS clock output, 2 EMACs, excellent hardened IP generally.
- azonenberg 2y agoI have some RT1176's in my "to try" pile. The big thing holding me back was that their crypto accelerators were all locked behind NDAs (a dealbreaker for F/OSS work) while the ST ones are documented in the freely downloadable datasheet you can just google up. But I did find some third party wrapper libraries that seemed to be able to use the crypto registers so it might be possible to figure things out from that. I haven't tried yet. The other issue I had with the RT is that they lacked internal flash so PCB complexity is slightly higher than with a STM32.
- 15155 2y ago> I have some RT1176's in my "to try" pile. Keep in mind the dual-core 11xx chips are a bit harder to boot than the rest of the line - but you probably need the power domain flexibility for most FPGA projects (1064 has way fewer practically-usable 1v8 banks.) > crypto accelerators were all locked behind NDAs I've been able to use every bit of hard IP and high-assurance boot from registers using no vendor code whatsoever. Here's what you are looking for: https://github.com/JayHeng/imxrt-level2-boot/blob/master/devices/MIMXRT1062/drivers/fsl_dcp.c https://github.com/JayHeng/imxrt-level2-boot/blob/master/dev... > The other issue I had with the RT is that they lacked internal flash The IMXRT1064 has a 4MB Winbond QSPI chip in-package, by the way! > PCB complexity is slightly higher than with a STM32. The Xilinx FPGA that is sitting next to your MCU incurs multiple orders of magnitude more PCB-complexity than a little QSPI flash, haha.
- dmitrygr 2y ago> 100K reads/writes of a 32-bit register You'll hit almost no bugs if you keep accessing the same address in a loop. Lucky you :)
- azonenberg 2y agoYeah but again, we're talking about the FMC here not the OCTOSPI. Have you hit issues with the FMC? From what other people are telling me, the OCTOSPI is full of land mines and the FMC is pretty decent. The worst errata I've encountered so far is two dummy clocks with CS# asserted at the end of a read burst.
- syntheticgate 2y agolol, I'm working on an FMC-FPGA interface at work right now and discovered this same chipselect behavior.
- azonenberg 2y agoIt's a documented errata, 2.6.1 on page 8 of ES0491.