alted

6 ms·

1.
by alted 10mo ago
The Hacker Fab [1] project at Carnegie Mellon is creating and publishing guides to building simple fab equipment including photolithography and a sputtering system. For somewhat more complex equipment, I appreciate [2] from the founders of
2.
by alted 2y ago
Ignoring flexibility and cost/performance, this may be a sign that rapid chip fab turnaround times are possible. These were made by Pragmatic Semiconductor [1], who claim they can make chips within 48 hours and deliver within 4 weeks (
3.
by alted 2y ago
Has anyone used Perforce Helix for this? If you're already using it for large file version control for, e.g., gamedev, and don't mind the cost, how well does it work to store all other company documents? I'd assume it has bet
4.
by alted 2y ago
Custom state-of-the-art silicon is ridiculously expensive. For a minimum 100 wafers = 10k chips, Groq may have paid $100M = $10k/chip purely in amortizing design costs. Chip design (software + engineer time) and fabrication setup (lith
5.
by alted 2y ago
Pragmatic is very impressive because they're a startup that (a) is building their own chip fab and (b) said fab is much faster and cheaper than existing fabs. They claim [1] to be able to make chips from a new design in only ~4 weeks c
6.
by alted 3y ago
Plasticity is interesting because it is maybe the only way to run the Parasolid geometry kernel natively on Linux right now. Parasolid, the library used to perform the geometric operations (the most difficult and important part of a CAD pro
7.
by alted 3y ago
Excellent question! A sufficiently advanced battery can theoretically beat gasoline. Any given energy storage technology can store a maximum amount of energy in a fixed volume or mass. Behold one of my favorite plots: [1] From lowest to hig
8.
by alted 3y ago
A disappointing fact of chip fabrication is the minimum bar is high and expensive. In other fields, a hobbyist can do wood/metalworking or learn programming or build a robot kit. There's an onramp for people to start learning the
9.
Zero to ASIC Course(zerotoasiccourse.com)
2 points by alted 3y ago|0 comments
10.
by alted 3y ago
Lower-level teaching resources definitely exist! Here are my favorites: - The Zero to ASIC course (and Tiny Tapeout) [1] explains transistor circuits and teaches you an open source software stack---and you get a chip physically manufactured
11.
by alted 3y ago
Cool project! Right now y'all look focused on digital logic somewhere between ASICs and FPGAs. Any plans for custom chiplets? Custom analog layout might be much cheaper if done MPW or Tiny Tapeout style: design a mere ~100x100um area,
12.
by alted 3y ago
I believe this is the Voxa Mochii [1]. [1] https://www.mymochii.com/
13.
by alted 3y ago
The probability may actually be much higher: about 12% per decade for a -850mT event; 1.5% for -1700mT [1]. Wikipedia estimates the Carrington was anywhere from -800 to -1750 [2]. [1] "On the probability of occurrence of extreme space
14.
by alted 4y ago
A common approach is to use multiple electron beams in parallel ([1] is up to 262144 beams!). This is starting to be used commercially to create the masks for photolithography. [1] https://www.ims.co.at/en/products&#x2F
15.
by alted 4y ago
I do research in a university lab that is also used by a number of companies. People make plenty of transistors, including state-of-the-art research. However, reasonably sized processors need millions of transistors, and (a) we can't e
16.
by alted 4y ago
Judging from [1], Sam Zeloof's plan might include using electron beam lithography, which scans an electron beam over a wafer surface, instead of normal photolithography. This can get high resolution (10nm) comparable with EUV, and coul
17.
by alted 4y ago
Fun fact: you may know silver (followed by copper) is the metal with the highest electrical conductivity at room temperature, but this is only true in bulk. When a piece of metal is thinner than 100nm or so, its conductivity increases basic
18.
by alted 4y ago
> the benefits are not as great as I think It's this one. You're probably thinking of an electrical insulator solely as a material with low conductivity. Vacuum, air, glass (SiO2) (which is the default insulator in chip manufac
19.
by alted 4y ago
A fun one with easy visualization is mechanical engineering statics, in which one calculates how much something deforms from a force (e.g., a bookshelf or bridge sags, a spring stretches, or an elastic tire or sponge or pillow squishes). Th
20.
by alted 5y ago
MEMS are awesome! Here are some other MEMS devices: - hard drive read/write heads (the platters are debatable) - inkjet printer nozzles (this is why making a DIY inkjet printer is nontrivial) - air pressure sensors (e.g., for car tires
21.
by alted 5y ago
The full setup is in the supplementary information (available at the bottom of the main paper website [1]), Figure 7. After this small lens, there are a couple more large lenses before the final camera/sensor, apparently an AVT Proscil
22.
by alted 5y ago
A WiFi/BT/NFC tag system has an antenna, and a radio circuit attached to the antenna. It's almost possible to inkjet print circuitry with transistors in research applications; see [1]. 20 micrometer resolution is relatively e
23.
by alted 5y ago
Nope. Since most manufacturing steps are performed on an entire silicon wafer at once, the cost per chip is cheaper if there are more chips on each wafer. As a result, wafers (for both basic and advanced chips) are filled with rectangular c
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by alted 5y ago
And it turns out DIY atomic force microscopes are possible too! (e.g., [1]) It's probably less likely to get all the way to atomic resolution (0.01nm) like a scanning tunneling microscope, but atomic force microscopes can take many typ
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by alted 6y ago
Previous discussion: https://news.ycombinator.com/item?id=24119102 ("3D Printing Integrated Circuits: What's Possible Now and in the Future?")
26.
by alted 6y ago
Apparently, it's possible to bend existing flat sensors! The backgrinding makes them thin enough to bend. Bending uses high-precision air pressure setups or something. [1] (This surprised me too, because manufacturing on silicon wafers
27.
by alted 6y ago
Yep! This is already done and for exactly this purpose; I believe the common term is "trusted timestamping" [1]. [1] https://en.wikipedia.org/wiki/Trusted_timestamping
28.
by alted 6y ago
Both FIB deposition and its cousin Focused Electron Beam-Induced Deposition (FEBID) are pretty nifty; they can cut/add materials down to maybe 1nm (!) resolution. However, they're extremely slow: they can only affect a single spot
29.
by alted 6y ago
Sure. Heidelberg's recently made [1] some cool tools ("maskless aligners") that can expose a ≈150mm wafer in an hour or so down to ≈500nm resolution, which is very convenient when rapidly iterating through one-off low-resolut
30.
by alted 6y ago
The best actually-printed-by-an-inkjet-printer circuits I know of are simple ring oscillators of at most ten transistors or so (e.g., [1]---and they're pretty bad transistors at that), and even the simplest microcontrollers require tho

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