adam_walker

5 ms·

1.
by adam_walker 3y ago
Yes, this is about building a small hashtable in the RAMs internal to the FPGA. As you pointed out, things would slow down a bit if you had to go to external RAM. However, if you are building a hashtable in external RAM that is accessed via
2.
by adam_walker 3y ago
Yup, and you can partition a FPGA in this way to scale the design to bigger chips.
3.
by adam_walker 3y ago
I'll have to think about that one. TBH, this stuff is pretty difficult to reason about. However, I can say that I used a SMT solver as part of the wonderful SymbiYosys verification flow to verify that the design was good for around 20
4.
by adam_walker 3y ago
Yes. My comment above glosses over some details. The SRAM clock and the Ethernet clock can be independent. The SRAM clock rate is what determines the rate of lookups for a single cuckoo hashtable. On a modern FPGA, the SRAM clock can run up
5.
by adam_walker 3y ago
Yes, benchmarks are missing. When I wrote this almost two years ago, I just wanted to explain the design at a high level to make it easier for people to understand the code. I didn't have access to a higher end FPGAs capable of 10G+ li
6.
by adam_walker 3y ago
> You'd be better off with a higher-level or more modern HDL that compiles to Verilog/VHDL. "Chisel" is one such. As is Clash, the language this project was written in :) https://clash-lang.org/
7.
by adam_walker 3y ago
Yes, but it would be if implemented on an FPGA with 10G capable transceivers. The hashtable is capable of looking up a key every clock cycle so it is actually capable of a fair bit more than 10G for lookups.