aappleby

27 ms·

1. 421.▲
   by aappleby 5y ago

   USB-C power delivery allows the device to request voltages other than 5v, up to 20v. Since the voltages differ, the ports cant all share one big 5v rail and need dedicated voltage converters. The power limits come from both the individual c
2. 422.▲
   by aappleby 5y ago

   And a not-inconsiderable number of people who will not be commenting here because they're dead.
3. 423.▲
   by aappleby 5y ago

   This is why you hire old programmers, so that you have someone to yell "WTF" when they see you have no testbench. We had that stuff figured out in the PS1 days.
4. 424.▲
   by aappleby 5y ago

   "In my case, I want to construct and call any shader I want at run-time. Arbitrary composition is the entire point. This implies that when I want to go make a GPU call, I need to generate and link a new program, based on the specific t
5. 425.▲
   by aappleby 5y ago

   The author seems to be assuming that the designers have never thought about this corner case.
6. 426.▲
   by aappleby 5y ago

   Yeah 4x4 would be a bit much, 3x3 is doable, 3x2 is easy.
7. 427.▲
   by aappleby 5y ago

   Surely it isn't that rare? I can track about 8 digits total while doing mental mul/div, and I don't think of that as anything special.
8. 428.▲
   by aappleby 5y ago

   Thanks for maintaining your SMHasher fork by the way, I've got too darn many other projects. :)
9. 429.▲
   by aappleby 5y ago

   Nice work. :D -Austin, author of Gateboy ( https://github.com/aappleby/MetroBoy )
10. 430.▲
    by aappleby 5y ago

    How many died because of lockdowns?
11. 431.▲
    by aappleby 5y ago

    Is that a problem?
12. 432.▲
    by aappleby 5y ago

    So in other words the Covid Pass is effective at preventing irresponsible people like the author from spreading a dangerous disease to others. Sounds good to me.
13. 433.▲
    by aappleby 5y ago

    "some kids are naturally better than others at doing tasks that school and future employers have deemed important" This characterization of "gifted" is so profoundly incorrect that I'm having trouble coming up with
14. 434.▲
    by aappleby 5y ago

    If only I could downvote you harder. :(
15. 435.▲
    by aappleby 5y ago

    700000+ is also a lot
16. 436.▲
    by aappleby 5y ago

    very silly. :)
17. 437.▲
    by aappleby 5y ago

    Code is read far more often than it is written. Optimize for readability.
18. 438.▲
    by aappleby 5y ago

    Sort of? It's almost more equivalent to networking or distributed processing - circuits in different clock domains can't just send a wire to another domain, they have to go through a synchronizer and do some handshaking and other
19. 439.▲
    by aappleby 5y ago

    They removed some instructions and added some instructions. Check the pandocs - https://gbdev.io/pandocs/
20. 440.▲
    by aappleby 5y ago

    Family tragedy and pandemic, no lie. Working on it kept me sane.
21. 441.▲
    by aappleby 5y ago

    FurrTek deserves as much credit as I do for doing the initial exceptionally painstaking step of marking out the die traces and cells on the die shot. Not all of his guesses were correct, but they were enough to get things started. I suspect
22. 442.▲
    by aappleby 5y ago

    wait, the repo on Github is just the read/write checker. I'll have to go find the translator...
23. 443.▲
    by aappleby 5y ago

    And it's mostly a proof-of-concept so don't expect much :)
24. 444.▲
    by aappleby 5y ago

    the Metron repo is on my Github but it's a horrendous embarassing mess.
25. 445.▲
    by aappleby 5y ago

    Easier than VHDL, harder than C. Chisel's "adder" example on the wikipedia page is: class Add extends Module { val io = IO(new Bundle { val a = Input(UInt(8.W)) val b = Input(UInt(8.W)) val y = Outpu
26. 446.▲
    by aappleby 5y ago

    SystemVerilog has enough C++-like _stuff_ in it that you can write a surprising amount of code that looks almost like C++ - you can call methods on objects, pass interfaces around, lots of other things that you might not immediately recogni
27. 447.▲
    by aappleby 5y ago

    As I understand it asynchronous logic stopped being a common thing decades ago, so those sorts of glitches aren't possible (or less possible?) now. The hard stuff in simulation now is probably handling multiple clock domains.
28. 448.▲
    by aappleby 5y ago

    The cores they have are more than good enough. I do intend to get GateBoy to where it can be automatically translated to Verilog though, at which point running on a FPGA should be more straightforward.
29. 449.▲
    by aappleby 5y ago

    I really think it should be, though I'd put a Risc-V RV32I core in place of the original one.
30. 450.▲
    by aappleby 5y ago

    You are quite welcome. :)