Easier than VHDL, harder than C. Chisel's "adder" example on the wikipedia page is: class Add extends Module { val io = IO(new Bundle { val a = Inp

Easier than VHDL, harder than C. Chisel's "adder" example on the wikipedia page is: class Add extends Module { val io = IO(new Bundle { val a = Input(UInt(8.W)) val b = Input(UInt(8.W)) val y = Output(UInt(8.W)) }) io.y := io.a + io.b } whereas the same in C would be uint8_t Add(uint8_t a, uint8_t b) { return a + b; } and while that is not directly usable in SystemVerilog, it can be mechanically translated to function byte add(byte a, byte b) return a + b; endfunction There's way more to it than that, but I strongly believe there are better ways of writing hardware than the existing HDLs.