_chris_

9 ms·

31.
by _chris_ 6y ago
Spoiler-alert, even your x86 desktop cores struggle to hit more than 1 IPC on most workloads. That's just the reality of cache misses, instruction dependencies, branch prediction, and more.
32.
by _chris_ 6y ago
The paper you linked to is about embedded controller micro-benchmarks being worse by 5-10%; RISC-V's compressed ISA made some tough decisions to improve density on general-purpose code, not just micro-focused on MCUs. On something larg
33.
by _chris_ 6y ago
There's a reason we wear shoes indoors in Texas...
34.
by _chris_ 6y ago
Slack is a lot better than Teams IMO, but it's hard to justify putting company stuff (like documentation and wikis) into a proprietary platform that could raise prices or disappear at any moment. With Teams, if you're already unde
35.
by _chris_ 6y ago
Register moves aren't free, even if you do renaming tricks. They take up fetch bytes, they take up decode slots, they take up a lot more resources than just Regfile/ALU bandwidth.
36.
by _chris_ 6y ago
> The variable length instructions of x86 mean you can fit more of them in an L1i of a given size. Unfortunately no, x86 is worse than RISC ISAs like ARMv8 and RISC-V in instruction density.
37.
by _chris_ 6y ago
>The 16 or 32 architectural registers of the ISA are pretty much irrelevant compared to the capabilities of the out-of-order engine on modern chips. This can have a big effect on memory traffic due to unnecessary moves and stack pops&#
38.
by _chris_ 6y ago
The problem is that providing extra bits for "sign-extension mode" and "read 32b or 64b" blows through the opcode space very quickly.
39.
by _chris_ 6y ago
Microsoft and I believe Qualcomm research took this and did two follow-on versions. They gave a joint keynote talk at ISCA (2018?) on their experiences, but I can't seem to find any slides or video on it. I recall them saying it looked
40.
by _chris_ 6y ago
Are they also open-sourcing the tool that generates the committed code? If not, then there's little difference between "generated" and "actual" source code.
41.
by _chris_ 6y ago
Being "simple" for a C program to decode is not the point; generating the smallest hardware to decode instructions and to reduce the critical path for things like deducing the instruction operands are. For example, the operands al
42.
by _chris_ 6y ago
> The game had been set to come out this year [me: March 2020], but the company said last month it was delaying the release until the fall of 2021. Is delaying the release by over a year and a half a win? I wonder how much in royalties
43.
by _chris_ 6y ago
Only speaking for myself, I think of FPGA and hw emulation interchangeably. At the end of the day, I don't care (or know) how it's implemented. What I can say is a) they aren't super fast, only ~1Mhz b) they take forever to c
44.
by _chris_ 6y ago
Great question. For starts though, you've just given me a list worth hundreds of trillions of instructions of tests. If you can actually test on an FPGA (which is usually not possible, and if it is, it's not representative of the
45.
by _chris_ 6y ago
> (B) I'm very much in a position where I can influence research in this direction. Could you elaborate on what you do? > Have you got any concrete ideas and proposals? My recommendation is: try to build something complex, or tak
46.
by _chris_ 7y ago
If you're willing to compromise on material, I believe Organic thin-film transistors (OTFT) can be patterned using printers! https://en.wikipedia.org/wiki/Organic_field-effect_transisto... Paper discussing charact
47.
by _chris_ 7y ago
My boss will never sign off on using a new language?
48.
by _chris_ 7y ago
Bought lots of frozen food and water (I should figure out how to do sugar water).
49.
by _chris_ 7y ago
To add to what you said, a 64 bit ARM ISA didn’t publicly exist yet when Berkeley started RISC-V.
50.
by _chris_ 7y ago
I’m sure it’s also about setting a precedent to current and future employees regarding leaving and starting new companies. What VC wants to spend their early money on lawsuits, even if you’ll (eventually) win?
51.
by _chris_ 7y ago
The wonderful thing about caches is that they are invisible to the programmer; the designer can add bigger caches, more levels of caches, different configurations of shared/private/inclusive/exclusive caches... and it Just Wo
52.
by _chris_ 7y ago
When you are selling IP like this you would need to do your own physical design due diligence, even if the deliverable is just some Verilog code.
53.
by _chris_ 7y ago
AIUI, the U5 series is BSD/open-sourced as "Rocket", and a version of their shared L2 cache is available as the sifive-inclusive cache. I believe Berkeley uses these artifacts as part of their FireSim ( https://fire
54.
by _chris_ 7y ago
End of an Era. She was incredibly helpful and kind in helping students navigate MIT and Course 6. It's going to take an entire department to replace her.
55.
by _chris_ 7y ago
You are confusing memory consistency with cache coherency.
56.
by _chris_ 7y ago
> "Cheap lo-fi art that looks good" is not a thing Dwarf Fortress was literally an exhibit in MOMA; it can look downright beautiful, despite being nothing but ASCII letters in different shades of colors: https://www.
57.
by _chris_ 7y ago
Great to hear he did his homework! Last I looked into this, AIUI, the default in the US is "everything the employee does the employee owns" (damn you wedding photographers!). So naturally, virtually every tech company contract wil
58.
by _chris_ 7y ago
"Hashed" in this case simply means they did some extra work to deal with the perceptron's XOR problem, since a straight mapping of PC and branch history would led to an inability to distinguish XOR patterns.
59.
by _chris_ 7y ago
First, most uops can't throw exceptions, so fusing a shift and an add instruction together doesn't require any complex tracking here. If a uop throws an exception (let's say a fused add+ld), each uop can have a tag that helps
60.
by _chris_ 7y ago
Designing a good vector ISA is really hard. The problem is "vector" is an entire category of architecture-style and machine designs; it's not a problem domain. So some people want vector for their very narrow domain (ML? IO

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