Peter_Sewell

3 ms·

1.
by Peter_Sewell 2y ago
Neither of these are actually the case: one doesn't need to be fluent in PL research to understand Sail specs (see @timhh comment above, forex), and Sail was developed independently of the origins of RISC-V.
2.
by Peter_Sewell 2y ago
Here is a piece of the Arm-A ASL: (result, -) = AddWithCarry(operand1, imm, '0'); if d == 31 then SP[] = ZeroExtend(result, 64); else X[d, datasize] = result; and here is some analogous Sail (automatic
3.
by Peter_Sewell 2y ago
Sail is pretty similar to ASL (both current ASL and ASL 1.0) except that (1) it has a more expressive type system, so that bitvector lengths can all be statically checked, (2) it has proper tagged unions and pattern matching, and (3) there&
4.
by Peter_Sewell 2y ago
There's increasingly mature work on CHERI temporal memory safety, eg https://www.cl.cam.ac.uk/research/security/ctsrd/pdfs/2020oa... and more recent versions.
5.
by Peter_Sewell 2y ago
If you want to narrow the bounds of `data` on reuse, you can do easily do that in CHERI C (you'd need to also keep the larger capability somewhere to rederive the `data` capability from, either in this struct or elsewhere, depending wh
6.
by Peter_Sewell 2y ago
CHERI enables a rather high level of memory safety. It uses dynamic hardware checks rather than the safe-Rust static checks, which means that existing C/C++ code can often be ported to CHERI C/C++ with minor changes. Of course, a
7.
by Peter_Sewell 6y ago
There's work along these lines (substantially predating Sail, but one could in principle do much the same starting from Sail specs) by Dias and Ramsey, e.g. the POPL 2010 and 2011 papers at https://www.cs.tufts.edu/~nr&