Marat_Dukhan

30 ms·

91.
by Marat_Dukhan 12y ago
Older gcc versions have `-ftrapv` option, which checks overflow for signed addition, subtraction, and multiplication. However, the implementation calls libgcc functions to do the checks, resulting in non-negligible overhead.
92.
by Marat_Dukhan 12y ago
nVidia GPUs with GM2xx chips (currently GeForce 900 Series)
93.
by Marat_Dukhan 12y ago
I wouldn't call Xeon Phi x86: - It doesn't support CMOV, MMX, SSE, AVX, and all other ISA extensions the popped up after the original Pentium. - It does not use standard System V x86-64 ABI. - Most of its compute power is due to s
94.
by Marat_Dukhan 12y ago
uop fusion was added in Pentium-M, the Pentium III modeled in the paper didn't have it.
95.
by Marat_Dukhan 12y ago
+ Hardware Transactional Memory that isn't buggy
96.
by Marat_Dukhan 12y ago
Here is the /proc/cpuinfo: processor : 0 cpu : POWER8E (raw), altivec supported clock : 3026.000000MHz revision : 2.1 (pvr 004b 0201) timebase : 512000000 platform : pSeries model : IBM pSeries (em
97.
by Marat_Dukhan 12y ago
Thanx for posting this info. The cpuinfo matches Marvell Armada XP.
98.
by Marat_Dukhan 12y ago
I think C++ should use notation similar to designated initializers (that C++ adapted from C99) for names arguments, i.e. rectangle->set(.x = 10, .y = 20, .width = 20, .height = 20) Otherwise, it would be very confusing that two different
99.
Benchmark of matrix-matrix multiplication in Web browsers(github.com)
2 points by Marat_Dukhan 12y ago|0 comments
100.
BLIS for the Web: High-Performance Computing in a Web Browser(cs.utexas.edu)
2 points by Marat_Dukhan 12y ago|0 comments
101.
Spec: JavaScript Shared Memory, Atomics, and Locks(docs.google.com)
6 points by Marat_Dukhan 12y ago|0 comments
102.
by Marat_Dukhan 12y ago
PowerPC A2 (Blue Gene/Q) and POWER 8 support hardware transactional memory as well
103.
by Marat_Dukhan 12y ago
SIMD.float32x4 and SIMD.int32x4 classes are available in Firefox Nightly, but without Float32x4Array and Int32x4Array loads and stores are horribly slow. About 100x slower than normal JavaScript in my tests.
104.
by Marat_Dukhan 12y ago
There are hints for taken/non-taken branches in x86. However, the only family to use them was Pentium 4; other processors silently ignore those hints. As for the write side, you'll find it here: https://opensource.apple
105.
by Marat_Dukhan 12y ago
One day the call instruction will cross cache line boundary, the two cache lines will propogate to other cores' instruction caches with a delay, some thread will try to execute partially changed call instruction, and some senior progra
106.
by Marat_Dukhan 12y ago
In the same context as "normal" decimal floating-point literals, e.g. double x = 0x1.ABCDEFp+89;
107.
by Marat_Dukhan 12y ago
Hexadecimal floating-point literals
108.
by Marat_Dukhan 12y ago
There are such options. Just use -mavx instead of -xAVX and it will compile for any AVX-compatible processor.
109.
by Marat_Dukhan 12y ago
Probably because Clang is the default compiler on Mac OS X, but not on Windows or Linux
110.
by Marat_Dukhan 13y ago
Visual C++ 2013 doesn't remove memset either.
111.
by Marat_Dukhan 13y ago
Yes, I compiled with -O3.
112.
by Marat_Dukhan 13y ago
I checked 3 compilers: icc 14, gcc 4.8, and clang 3.3. Clang is the only one which optimized the memset away.
113.
by Marat_Dukhan 13y ago
The author probably thinks that all versions are equally fast, but in fact they are just equally slow. Neither gcc 4.8 nor icc 14 can use vectorization for this loop (likely because of aliasing).
114.
by Marat_Dukhan 13y ago
This is neat, but please add a pointer to deallocation function to sds header and use it in sdsfree. This will allow to return sds strings from functions in shared libraries. A common problem it that the user of the library might use a diff
115.
Yeppp! a trivial test(nosubstance.me)
1 points by Marat_Dukhan 13y ago|0 comments
116.
by Marat_Dukhan 13y ago
Thank you! Please let me know if you run into issues about using Yeppp! with your project.
117.
Show HN: Open-source SIMD-accelerated math library for C/C++/C#/Java/FORTRAN(yeppp.info)
9 points by Marat_Dukhan 13y ago|3 comments
118.
by Marat_Dukhan 13y ago
The 3-cycle latency refers to simple NEON ALU instructions (VADD.Ix, VORR, VAND, etc). Scalar ALU instructions are still single-cycle. Note that these numbers are from Cortex-A15 and Krait which are expected to be similar to Swift, but I di
119.
by Marat_Dukhan 13y ago
Wow, amazing performance tuning, so rare these days! However, you should be careful with this online ARM simulator. It simulates Cortex-A8 while iPhone 5 runs on Apple Swift, two generations ahead. It very likely has different instruction t
120.
Intel AVX-512, SHA, and MPX (Memory Protection) instruction extensions(software.intel.com)
1 points by Marat_Dukhan 13y ago|0 comments

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