Marat_Dukhan

9 ms·

31.
by Marat_Dukhan 9y ago
CPU INFOrmation library: a cross-platform library to discover supported instruction sets, microarchitecture, and cache parameters of the CPU. Started as a "oh, I can do it over the weekend" project at first, took close to a year t
32.
by Marat_Dukhan 9y ago
There is transfer time. You source image is in cacheable CPU memory. Integrated GPUs normally work with uncacheable memory allocated in a special region of system memory. Some GPUs can access cacheable memory too, but it is much slower (bec
33.
by Marat_Dukhan 9y ago
It should, if you find that converted model doesn't work, it is a bug, please file it with PyTorch and/or Caffe2. Implementation details of course differ between frameworks, but luckily neural networks are very robust to noise. In
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by Marat_Dukhan 9y ago
Reference specification and validator are hosted in https://github.com/onnx/onnx
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by Marat_Dukhan 9y ago
Have you looked at ONNX? It is a neural network exchange format that, in particular, lets you deploy PyTorch models in production via Caffe2. Here is a tutorial: http://pytorch.org/docs/master/onnx.html Disclaimer
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by Marat_Dukhan 9y ago
Interestingly, amazon.feedback redirects to amazon.com, so Amazon did pay
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mInference demo: ImageNet convnets inside a Web browser (WAsm/Asm.js/PNaCl)(minference.com)
1 points by Marat_Dukhan 9y ago|0 comments
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by Marat_Dukhan 9y ago
Russian social network Odnoklassniki ("classmates" in English) tried subscription-based model for two years. It nearly killed them.
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by Marat_Dukhan 9y ago
I made a Python package which documents x86(-64) instructions in a ready-to-use way: https://github.com/Maratyszcza/Opcodes (also `opcodes` on PyPI). With this package, its easy to collect ISA stats, e.g. import op
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by Marat_Dukhan 9y ago
Right, needs brackets: lambda (a, b)
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by Marat_Dukhan 9y ago
Yes, lack of implicit tuple unpacking in lambda is what forces me to write `lambda a_b`. Python 2.7 has imap and ifilter in itertools. Python 3 could have imported them into global namespace to simplify usage without breaking map/filte
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by Marat_Dukhan 9y ago
Yes, sets are mutable, but if I call dict.keys, I expect to get a copy of keys.
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by Marat_Dukhan 9y ago
lambda a, b: a + b kind of works, but you can't call it with tuple argument (which you could in Python 2.7). This hurts when e.g. you have a list of pairs and try to map when via lambda, e.g.: map(lambda a, b: a+b, [(1, 2), (3, 4)]). E
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by Marat_Dukhan 9y ago
Because Python 2.7 is, IMO, a better language than Python 3+, e.g.: - I like lambda a, b: a + b syntax better than lambda a_b: a_b[0] + a_b[1] - I prefer map/reduce/filter to return lists rather than iterable - I prefer dict.keys&
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by Marat_Dukhan 9y ago
PeachPy, an x86-64 assembler in Python, is often used to target Golang assembler without dealing with its weird syntax. PeachPy uses Intel assembly syntax, but can generate assembly listing for Golang toolchain as its output. Damian Gryski
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by Marat_Dukhan 10y ago
Oops, here is the actually used vectorized expf (similar to the one I linked, but with optional unrolling): https://github.com/Maratyszcza/NNPACK/blob/master/src/x86_64...
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by Marat_Dukhan 10y ago
This is the reference implementation of softmax, i.e. implementation used as a reference in unit tests. It is designed to be simple, readable, and correct, which is why I linked it here. Optimized implementation is in assembly (PeachPy). Se
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by Marat_Dukhan 10y ago
If you have an efficient vectorized implementation of expf (NNPACK does), softmax is a memory/cache bandwidth-bound kernel, and storing data is less efficient than recomputing.
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by Marat_Dukhan 10y ago
>>> Softmax can be implemented as a composition of primitive TensorFlow ops (exponent, reduction, elementwise division, etc.): softmax = exp(logits) / reduce_sum(exp(logits), dim) No, it can not be implemented this way, it is
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by Marat_Dukhan 10y ago
Google Native Client is not deprecated, it is still supported in Chrome, and in many ways exceeds the capabilities of WebAssembly. WebAssembly is very different, and in Chrome it is implemented on top of TurboFan, V8's code generator,
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by Marat_Dukhan 10y ago
I thought refresh rate is programmable. But if not, at least firmware could lower the DRAM frequency. Intel GPUs have write-back caches because they share L3 cache with CPU cores. AFAIK, other GPUs typically have write-through caches, which
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by Marat_Dukhan 10y ago
I don't see how it will help. First, if the vendors can ship a new Linux kernel, they can as well ship updated firmware to increase memory refresh frequency. Secondly, on mobile devices CPU and GPU share the same memory, and it could b
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NNPACK – acceleration package for neural networks on multi-core CPUs(github.com)
8 points by Marat_Dukhan 11y ago|1 comments
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by Marat_Dukhan 11y ago
Peachpy.io is a work-in-progress...
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by Marat_Dukhan 11y ago
I am working on http://www.peachpy.io (an academic project) which lets performance tuning experts optimize assembly kernels for various x86-64 microarchitectures. We currently have Intel Nehalem, Intel Ivy Bridge, Intel Haswell,
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by Marat_Dukhan 11y ago
Wow, this is very nice! I use UptimeRobot for one of my projects, and it took me several hours to set up the tests there. And now I configured the same tests on ping-api in just few minutes!
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by Marat_Dukhan 11y ago
I guess that's because unlike AMD, nVidia doesn't officially document the GPU instruction set. But if you disassemble .cubin with nvdisasm, you'd see that code of Kepler/Maxwell is organized in bundles of 4/8 words,
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by Marat_Dukhan 11y ago
The latest number I have is 157 bits in Intel Core (for a ROB entry).
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by Marat_Dukhan 11y ago
I think SIMD.js need more operations, which may not directly map to hardware, but are "at least no worse than what applications would do otherwise": 1. The most obvious operation is multiply-accumulate, which would map to either m
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by Marat_Dukhan 11y ago
No they aren't internally RISC. On big Intel & AMD cores "ADD reg, mem" translates to a single uop. On Intel Atom even "ADD mem, reg" translates to a single uop. In fact, it is mostly legacy instructions (e.g. b

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