DrHoppenheimer

4 ms·

1. 1.▲
   by DrHoppenheimer 11y ago

   Multi-die FPGA packages are a giant PITA to deal with, compared to monolithic. It's a lot harder to resolve timing problems. There's a small customer base that's already used to partitioning their designs across multiple FPGA
2. 2.▲
   by DrHoppenheimer 11y ago

   You're confusing OpenCL with high level synthesis (HLS). OpenCL is explicitly a platform for software developers. It targets accelerator boards attached to a host (via PCIE), just like GPGPU. https://www.altera.com/solu
3. 3.▲
   by DrHoppenheimer 11y ago

   That's not how it works, actually. The compiler generates the dataflow directly in hardware.