Const-me

12 ms·

181.
by Const-me 2y ago
> That includes HN I think when people say “algorithmic sorting” they usually mean an algorithm which generates different, “personalized” sort order for different users.
182.
by Const-me 2y ago
About rendering triangle meshes with compute shaders, here’s a long technical video how UE5 does that: https://www.youtube.com/watch?v=TMorJX3Nj6U&t=3488s
183.
by Const-me 2y ago
> required Assembly programming Demoscene skill level to make good use of them Yeah, but writing efficient CUDA kernels, or D3D compute shaders, is not particularly straightforward either. At least GPU cores have direct access to global
184.
by Const-me 2y ago
> the nonsense of Larrabee/making it out of x86 It only seems nonsense in retrospect. No one expected nVidia to improve flops/dollar in their GPUs that quickly. And Larrabee wasn’t the only architecture deprecated by GPGPUs, Ce
185.
by Const-me 2y ago
Java and C# runtimes are getting memory safety at the cost of RAM usage in runtime, to lesser extent CPU overhead in runtime. Rust is getting memory safety at the cost of cognitive load of developers. Due to this tradeoff, by design Rust is
186.
by Const-me 2y ago
The scrolling doesn’t work in my MS Edge so I opened the page in Firefox. Firefox has “Open Video in New Tab” context menu command. When viewed that way, the videos are not that impressive. Horrible visual quality, Egyptian pyramids of rand
187.
by Const-me 2y ago
> Programmers have a predictable response to that sort of silliness. Build a library over it & abstract it away Impossible. GPGPU runtimes are too close to hardware, and the hardware is proprietary with many trade secrets. You need s
188.
by Const-me 2y ago
For marine applications, I think propane fuel cells will work better than batteries. Unlike batteries, energy density of liquified propane is good. Unlike hydrogen, logistics of propane is solved by now as it’s already widely used to fuel v
189.
by Const-me 2y ago
> custom Oryon ARM cores they got from the Nuvia acquisition Nuvia was developing server CPUs. By now, I believe backward compatibility with x86 and AMD64 is rather unimportant for servers. Hosting providers and public clouds have been o
190.
by Const-me 2y ago
> Qualcomm didn't implement TSO in the chips they made I’m not sure they can do that. Under Technology License Agreement, Qualcomm can build chips using ARM-designed CPU cores. Specifically, Qualcomm SQ1 uses ARM Cortex A76/A55
191.
by Const-me 2y ago
When I needed something similar to that for older Linux kernels, I have used primitives based on file descriptors (eventfd for manually reset events, pidfd_open to wait for completion of processes, mq_open for sending messages), and poll()
192.
by Const-me 2y ago
> For 969 tok/s in int8, you need 392 TB/s memory bandwidth I think that math is only valid for batch size = 1. When these 969 tokens/second come from multiple sessions of the same batch, loaded model tensor elements are r
193.
by Const-me 2y ago
The article seems specific to JavaScript, C# is different. > you cannot await in a sync function In C# it’s easy to block the current thread waiting for an async task to complete, see Task.Wait method. > since it will never resolve, y
194.
by Const-me 2y ago
Yeah, that algorithm is pretty good. BTW, when I needed it, I have ported C algorithm from fontstash library to C++: https://github.com/Const-me/nanovg/blob/master/src/FontStash...
195.
by Const-me 2y ago
> I think Rust strikes a pretty good balance with it though I don’t like that balance. For performance-critical things like BLAS and other low-level numerical stuff, C++ is safer than unsafe Rust because standard library and tooling (deb
196.
by Const-me 2y ago
> rules out a relatively small subset of architectural choices which are arguably a bad idea anyways Just because an algorithm is not representable in safe rust doesn’t mean it’s a bad idea. See my other comment in this topic https:&#x2
197.
by Const-me 2y ago
> I've written a ton of software, both backend and embedded-like software in C++ Me too. > What are people writing that requires such fancy/extensive usage of the borrow checker? The simplest example I can imagine is this:
198.
by Const-me 2y ago
> it makes you architect your programs and consider that ahead of time This only works for projects which do not involve any R&D, but have a complete and well written functional specification written in advance. Also for projects whi
199.
by Const-me 2y ago
> The kind of bug I was trying to add exists in many languages Any example except C++? BTW, the closest thing possible in C# is modifying a collection from inside foreach loop which iterates over the collection. However, standard library
200.
by Const-me 2y ago
BTW, it’s the same for GPUs. In DXBC shader byte code, mad instruction does FMA. When reporting theoretical FLOPs, GPU vendors count that as 2 float operations. For example, I have GeForce 4070 Ti Super in my desktop. The chip has 8448 exec
201.
by Const-me 2y ago
One FMA counts as two floating-point operations: one multiplication and one addition. According to uops.info, Zen 4 cores can do two 8-wide FMA instructions per cycle, or one 16-wide FMA per cycle. See VFMADD132PS (YMM, YMM, YMM) and VFMADD
202.
by Const-me 2y ago
I wasn’t aware there’re two completely different things from different companies both called AMX. I assumed that AMX: https://en.wikipedia.org/wiki/Advanced_Matrix_Extensions The Apple’s version is indeed interesting.
203.
by Const-me 2y ago
One interesting thing about these newfangled matrix/AI/ML accelerators that’s very rarely mentioned on the internets, they only deliver that many TFLOP because they operate in very low precision. nVidia tensor cores support int8,
204.
by Const-me 2y ago
Yeah, but not on a single core. In my desktop computer, I have Ryzen 7 8700G CPU, which has 8 Zen 4 cores, 4.2 GHz base frequency, 65W TDP. Theoretically, when doing FP32 FMA, each CPU core can do 32 FLOP/cycle. At the base frequency,
205.
by Const-me 2y ago
Sorry, I have not benchmarked against cuBLAS or Eigen or similar, I did that thing for ML inference. I have implemented a profiler on top of D3D11_QUERY_TIMESTAMP and D3D11_QUERY_TIMESTAMP_DISJOINT queries, and tweaked the compute shader to
206.
by Const-me 2y ago
OP implemented that stuff with WebGPU. In runtime, that weird language compiles into a compute shader which computes that stuff on GPU.
207.
by Const-me 2y ago
> you can reach ~75% of peak performance for same matrix config Not on the same computer, CUDA doesn’t run on the integrated GPU of the Apple M2 Pro.
208.
by Const-me 2y ago
> don't have support for hardware specific memory I have no experience with WebGPU but if you mean group shared memory, I think the support is available. See the demo: https://compute.toys/view/25
209.
by Const-me 2y ago
Couple years ago, I wanted about the same thing in HLSL language, for a Direct3D 11.0 compute shader. Here’s the fastest version I managed to make back then: https://github.com/Const-me/Cgml/blob/master/M
210.
by Const-me 2y ago
> none of the major APIs expose a 1-bit texture format AFAIK so R8 would be the next best thing I think the next best thing is BC4. The compressed format stores 8 bits/pixels grayscale texture compressed into 8 bytes / 4x4 pixe

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