CalChris

58 ms·

1. 901.▲
   by CalChris 5y ago

   neovim 0.5 is not quite out (but it's real close). https://github.com/neovim/neovim/milestone/19 I've been using a neovim nightly along with VSC and Alexey Svetliakov's Neo Vim extension. His e
2. 902.▲
   by CalChris 5y ago

   Hennessy + Patterson, Computer Organization and Design, ARM edition https://www.elsevier.com/books/computer-organization-and-des...
3. 903.▲
   by CalChris 5y ago

   I'm a road biker and not a mountain biker but I do have bar ends on my urban bikes and bar ends are great for control and leverage, at least for me. But I don't get that. How is it any more likely to catch a bar end on a branch th
4. 904.▲
   by CalChris 5y ago

   Security claims will always depend on a threat model. The question doesn't provide a threat model. So the answer's proviso is appropriate.
5. 905.▲
   by CalChris 5y ago

   All coins are Ponzi schemes. Tether is a coin. Tether is a Ponzi scheme.
6. 906.▲
   by CalChris 5y ago

   Those ships still have to enter the harbor and then have to be unloaded. The Benjamin Franklin has a 52 foot draft and stacks containers 10 high [1]. That means deeper dredging and bigger cranes. She called on LA, Oakland and Seattle but
7. 907.▲
   by CalChris 5y ago

   Aluminum is the third most abundant element after oxygen and silicon in the earth's crust. Lithium is the 25th most abundant element. Early days, but that might bring cost down.
8. 908.▲
   by CalChris 5y ago

   It is a coin battery and the Apple AirTag uses a CR2032. It was probably a simple misquote.
9. 909.▲
   by CalChris 5y ago

   Well, it has one: FJCVTZS Floating-point Javascript Convert to Signed fixed-point, rounding toward Zero .
10. 910.▲
    by CalChris 5y ago

    AnandTech says there is one separate integer division unit in the A14 Firestorm which is what the M1 is based on. The article even mentions an increase in latency for integer division for the A14. https://www.anandtech.com&#x
11. 911.▲
    by CalChris 5y ago

    I do and my assembler is clang. .intel_syntax
12. 912.▲
    by CalChris 5y ago

    What about the voice command “Turn on windshield wipers” ?
13. 913.▲
    by CalChris 5y ago

    I’ve read that data + power can share a wire at 48v, powered Ethernet.
14. 914.▲
    by CalChris 5y ago

    I understand Musk’s point on parts not being available now (then? Model 3) but I’d like to see a deep dive on 48v vs 12v.
15. 915.▲
    by CalChris 5y ago

    My sister's a doc. Same anecdote. She had a patient who fell at home while severely weakened with COVID. Death certificate did not say COVID.
16. 916.▲
    by CalChris 5y ago

    I think the RISC-V Vector Extensions are very elegant. However, I'm more interested in what hard core practitioners think and the ones I follow are nonplussed. https://gist.github.com/erincandescent/8a10eeeea1918ee
17. 917.▲
    by CalChris 5y ago

    Yes. I saw a presentation by the CEO of Western Digital. He was dressed in a polo shirt and blue jeans. But he was in fact very well dressed and if I were in a Brooks Brothers suit, he would have looked more professional. His presentation w
18. 918.▲
    by CalChris 5y ago

    The associated video tutorial: https://www.youtube.com/watch?v=56IIrBZy9Rc&t=13s
19. 919.▲
    by CalChris 5y ago

    How is this different from prelink? https://linux.die.net/man/8/prelink
20. 920.▲
    by CalChris 5y ago

    fvi - find vi - recursively grep for a pattern and pass the successful files into the editor. I use this to find examples in a codebase. Sure, it would be nice to set editor's pattern and have it jump to the first occurrence but that h
21. 921.▲
    by CalChris 5y ago

    Jevon’s paradox https://en.m.wikipedia.org/wiki/Jevons_paradox#Khazzoom–Broo...
22. 922.▲
    by CalChris 5y ago

    They've tried variations of this. It takes instruction bits to describe these registers: 32 regs is 5 bits, target + src1 + src2 is 15 bits already. They've tried scratch pads. The Mill CPU's Belt is yet another approach.
23. 923.▲
    by CalChris 5y ago

    Because Miami.
24. 924.▲
    by CalChris 5y ago

    I have no idea why fixups cause less sharing. I get this now. The fixups are runtime patches for call addresses in the application code to point to where the shared library function was mmap() 'd. Those patches, although they will a
25. 925.▲
    by CalChris 5y ago

    That application wasn't updated, full stop.
26. 926.▲
    by CalChris 5y ago

    The purpose of register renaming in the AArch64 microarchitectures is to support out-of-order . By comparison, you don't find register renaming in the in-order A53. https://en.wikichip.org/wiki/arm_holdings&#x2F
27. 927.▲
    by CalChris 5y ago

    Thanks, I've always thought of fixups as being a linker thing [1]. But I guess it's more general than that. [1] https://llvm.org/doxygen/classllvm_1_1MCFixup.html
28. 928.▲
    by CalChris 5y ago

    I like this (shared libraries are mindlessly overused) but there were two points I didn't understand. And the memory savings are often actually negative Not sure but I think this is for a library with only a single user (ever)
29. 929.▲
    by CalChris 5y ago

    The paper: I See Dead µops: Leaking Secrets via Intel/AMD Micro-Op Caches http://www.cs.virginia.edu/venkat/papers/isca2021a.pdf
30. 930.▲
    by CalChris 6y ago

    ... to captains not deviating from a storm to save on fuel and time as they face pressure from charterers ... Rather than shifting this cost to the shippers, they are essentially shifting it to the insurers and then paying more in premium