BrannonB

3 ms·

1. 1.▲
   by BrannonB 8y ago

   Your second point was that HW engineers haven’t learned about sharing—as evidenced by the fact that they use a different term for it than SW does. Again this is evaluating HW through a SW prism. Where’s github for bridge designers? rocket s
2. 2.▲
   by BrannonB 8y ago

   25 years of high performance chip design. Perhaps you’re an FPGA guy? The tradeoffs are different in that world.
3. 3.▲
   by BrannonB 8y ago

   If you think Verilog is bad, you should see the languages used by heart surgeons, civil engineers and rocket scientists. The language of human biology is ridiculously verbose without even a hint of polymorphism. ;-) My point is that it&#x27