4 ms·

Interrupts / Exceptions are probably the most difficult piece and may force a complete redesign. Since they are not done yet, I'd wait a little bit longer...

• _chris_ 11y ago
  It's actually really pretty easy to do. I put together a handful of different RISC-V cores that all implement the privileged/supervisor spec (https://github.com/ucb-bar/riscv-sodor/blob/master/src/rv32_1stage/cpath.scala https://github.com/ucb-bar/riscv-sodor/blob/master/src/rv32_...). Basically, detect a few cases in Decode, pass the rest of the instruction down the pipeline to the commit(memory) stage, and let the commit stage detect exceptions and redirect the PC as required.
  • inforichland 11y ago
    Exactly, that's how I would (hopefully will soon) implement it as well; it takes a few extra cycles but avoids extra overhead.
• sklogic 11y ago
  or1k used a very simple approach - duplicate all the pipeline registers in all the stages and use two register files. Then store the current state once interrupt is raised and restore when handler done working. This design can be easily derived from an existing one.