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3D Xpoint memory: Faster-than-flash storage unveiled
- deleted 11y ago[deleted]
- Splendor 11y agoSo this is essentially persistent DRAM?
- ericd 11y agoThat's certainly what it sounds like, at least in terms of functionality. Slightly slower, non-volatile RAM.
- nick-parker 11y agoThe article mentions: >By contrast, 3D XPoint works by changing the properties of the material that makes up its memory cells to either having a high resistance to electricity to represent a one or a low resistance to represent a zero. Which sounds a lot like memristors: https://en.wikipedia.org/wiki/Memristor https://en.wikipedia.org/wiki/Memristor to me. If it's memristor memory, the main advantages are that it's cheap, uses hugely less power than flash, takes up less space, and has far lower latencies. We're probably a long ways from replacing DRAM with memristors because it's still much higher latency, but if this stuff scales up well you could do something like put the whole page file on it and get even faster loads than current top of the line SSDs.
- digikata 11y agoThe press release seems to be intentionally silent on the actual memory cell technology. Another possible tech the cell might be based upon is some variant of Nano-RAM. https://en.wikipedia.org/wiki/Nano-RAM https://en.wikipedia.org/wiki/Nano-RAM
- higherpurpose 11y agoI assume there are some other disadvantages besides just a high price compared to either DRAM or SSD storage. What are they?
- swalsh 11y agoFrom the article "Each megabyte of 3D Xpoint will certainly be significantly cheaper than the equivalent amount of Ram. And the new technology has the added advantage of being non-volatile, meaning it does not "forget" information when the power is switched off. But, unfortunately it is still not quite as fast as Ram, and some - but not all - applications need the extra speed the older tech provides."
- acqq 11y agoIf what they claim is true, it has the potential to be actually cheaper than both DRAM and NAND, based on the density. The biggest disadvantage at the moment is that is so new that we don't know much. What can be read from the announcement: it's not as rewritable as DRAM: only up to 1000 more writes than NAND. It's also slower than DRAM. But it seems better than NAND in all aspects.
- DasIch 11y ago
- anotherangrydev 11y agoAlways the same thing. >1000X faster, 1000X cheaper! Then "No, you can't buy one right now, but you will be able to do it "soon". And, no it won't actually be 1000X faster neither 1000X cheaper because blah blah blah..."
- DasIch 11y agoThey explicitly mention that they are going to release it next year. Not exactly when next year but it's clear enough of a statement that it will be a public failure, if they don't come out with it. I think that's sufficient to not put it into the vaporware category.
- anotherangrydev 11y agoOver the years I have come to realize that unless I can buy something in the nearest BestBuy/Amazon, it is vapor. And also, until then, I would know how much cheaper and better performant it actually is.
- yokohama11 11y agoIt's an official press release from Intel and Micron and the release says that they've begun production, not that they just got it working in a lab. Performance questions are more valid.
- simpsond 11y agoOn the infographic the subtext of "1000x faster" is "up to 100s of times faster than NAND" Then it mentions 10x more performance with a PCIe/NVMe interface. Still all good things, but 1000x is probably more marketing than reality. Source: http://www.intelsalestraining.com/infographics/memory/3DXPointc.pdf http://www.intelsalestraining.com/infographics/memory/3DXPoi...
- williadc 11y agoMy guess is that 10x indicates that they've saturated the bandwidth of the PCIe interface.
- minthd 11y agoA guess: this uses memristors(i.e. rram). crossbar is a startup in the field, their site gives plenty of details about the tech. http://www.crossbar-inc.com/ http://www.crossbar-inc.com/
- simpsond 11y agoDo memristors read or write based on the applied voltage? I noticed that in some of the intel marketing material.
- p1esk 11y agoHow else would you do read/write?
- simpsond 11y agoI'm not familiar with the physics of memristors or storage in general. I was wondering if a single line is used to read and write, increasing the voltage on write to change the state.
- kragen 11y agoApparently a few different things have been called "memristors", but at least some of them have a resistance that depends upon the integral of current through them into the infinite past. DC current one way to write a 1, the other way to write a 0, and AC current to nondestructively read, I guess. Typically this works through ion migration in the material, and I suspect that resulted in abysmal endurance, putting an end to the promise of memristors.
- kken 11y agoRRAM was there first, and it will previal. Lets just forget about this "memristor" PR-nonesense. HP did as well. (Their activities seem to be dead)
- faragon 11y agoI think this is not the memristor thing. I remember memristor-related posts in Slashdot (2008 [1], 2012 [2]), but the ones related to Intel + Micron (2014 [3], 2015 [4]) tell about "3D nand", which may be just NAND-flash using multiple layers with 3D interconnect. However, the speed and density claims make doubt if in reality this is or not the same as the memristor. [1] http://hardware.slashdot.org/story/08/04/30/211228/memristor-4th-basic-element-of-circuits http://hardware.slashdot.org/story/08/04/30/211228/memristor... [2] http://hardware.slashdot.org/story/12/07/25/2127229/the-hp-memristor-debate http://hardware.slashdot.org/story/12/07/25/2127229/the-hp-m... [3] http://hardware.slashdot.org/story/14/11/25/2027220/how-intel-and-micron-may-finally-kill-the-hard-disk-drive http://hardware.slashdot.org/story/14/11/25/2027220/how-inte... [4] http://hardware.slashdot.org/story/15/03/26/2037221/micron-and-intel-announce-3d-nand-flash-co-development-to-push-ssds-past-10tb http://hardware.slashdot.org/story/15/03/26/2037221/micron-a...
- fahim305 11y agoSamsung had similar claims about v-nand/3D-nand, which they released on their 850 Pro series
- adsr 11y agoI hope someone will give a push behind MRAM which seems like a more interesting option imo. MRAM has similar performance to SRAM, similar density to DRAM but much lower power consumption than DRAM, and is much faster and suffers no degradation over time in comparison to flash memory. It is this combination of features that some suggest makes it the “universal memory”, able to replace SRAM, DRAM, EEPROM, and flash. https://en.wikipedia.org/wiki/Magnetoresistive_random-access_memory#Overall https://en.wikipedia.org/wiki/Magnetoresistive_random-access...
- aidenn0 11y agoI'd like to see a source for the "similar density to DRAM" my understanding is that it's an 8F2 footprint, and scaling it down to small process nodes is still problematic, even with spin-torque transfer. All that being said, there are people who make the exact same claims about RRAM as you quote for MRAM, which 3d-xpoint appears to be. Also note that you can buy MRAM parts right now, which are replacements for battery-backed SRAM, and are more radiation resistant than SRAM. Densities are fairly low though.
- adsr 11y agoFair point, perhaps I should have phrased it more as a technology with similar applications. I find it interesting that there are parts available now, albeit made on a 180nm process apparently.
- the8472 11y agothese guys claim 55nm mram: http://www.avalanche-technology.com/about/public-relations http://www.avalanche-technology.com/about/public-relations
- the8472 11y ago> my understanding is that it's an 8F2 footprint Where does that come from? From everything I've read is that its structure is fairly analogous to DRAM, "simply" replacing the capacitor with the magnetic tunnel junction, which has its component layers stacked vertically, thus not really taking up any extra space. > scaling it down to small process nodes is still problematic, even with spin-torque transfer. yeah, that's the main gist I'm getting too from following the news. > people who make the exact same claims about RRAM as you quote for MRAM, which 3d-xpoint appears to be. At least the xpoint incarnation still seems to be slower than DRAM according to that article, while MRAM is being offered as SRAM/battery-backed DRAM drop-in replacement.
- tmd83 11y agoThe biggest thing that just came to my mind is for durable storage. I think I can some problem at work radically differently and much simpler if I had this available in 10s of GB. How? Because its bit addressable and persistent. Together this makes it much simpler to implement some durable storage . We don't need the log structure good for NAND block erase issue. We don't need to worry about the flush cost compared to HDD (and this ones even faster than NAND). It would be simple to batch write the data to a slower storage if the Xpoint memory fills up. You can design databases that keep the hot data in memory and merge the result with older disk storage and this would allow a lot of batching for efficient processing and storage. But given its a database/transaction you need durability and that makes thing that much complicated. There are still lots of problem to solve when you cross the limit of a single machine but the single machine limit can get a lot larger for a lot of problems.
- wtallis 11y agoThey're claiming three orders of magnitude faster than NAND and three orders of magnitude more durable than NAND, which means you'll still need wear leveling to get it to last for several years, but you apparently won't have the complexity of erase blocks being much larger than writable page size. I do wonder how much it would be slowed down by the kinds of sophisticated error correction SSDs are now relying on.
- rosser 11y ago"Bit-addressable". I don't think this suffers from the same issues that NAND does with successive writes. The other articles I'm seeing after a quick search also suggest a three order of magnitude increase in write endurance.
- wtallis 11y agoYes, if you read what I wrote I mentioned the three orders of magnitude increase in write endurance as compared with NAND. But when paired with the three orders of magnitude increase in performance, that means it takes the same number of hours to burn it out. And a NAND device without wear leveling can be burned out in less than a day of heavy use. Bit addressability has absolutely nothing to do with endurance. NOR flash is bit addressable but suffers from the same endurance limitations as NAND, because they're fundamentally the same kind of memory cell, just connected differently.
- Animats 11y agoSo what do we do with it? We have two models of storage - volatile working storage, and things that simulate disk drives. It's not clear what to do with persistent randomly addressable storage at DRAM speed. Having to go through an OS and a file system to access a few bytes kills the performance advantage of such devices. Making the device look like RAM makes it too easy to mess up. We need something in between, probably with processor support to allow controlled access without going through the OS for each access. The great thing about RAM being volatile is that you can reboot and clean up your mess. With persistent storage, things can go gradually downhill.
- Someone 11y agoUse the MMU to keep the fast non-volatile RAM out of both application and kernel memory, put a traditional RAM disk file system on the fast non-volatile RAM, and let mmap truly map blocks of files into address spaces, instead of demand-paging it in. That probably is not the best one can do, but it is simple, and may be fairly easy to get ‘right’ if you put the code handling the file system part into a secondary kernel address space. That keeps the part that can mess up the file system’s metadata small.
- stellarhopper 11y agoDAX, which is already in new kernels, provides something like this. https://lwn.net/Articles/610174/ https://lwn.net/Articles/610174/
- nly 11y agoI think the only distinction you need to make is memory where transactions make sense (user data), and where they don't (program state). I can see a scenario where opening a file for writing works just like mmap[0] with MAP_PRIVATE, i.e. you get blockwise copy-on-write, except everything will persist as if everything on your filesystem was under a VCS like git. I reckon just like volume management, encryption and snapshotting has steadily been folded in to the filesystem, so will the VFS and page cache. [0] http://man7.org/linux/man-pages/man2/mmap.2.html http://man7.org/linux/man-pages/man2/mmap.2.html
- mmf 11y agoI did research in the field from 2008 to 2013. The claims are always the same: faster than flash, denser than dram, lower power than both. Here's how to spot BS: first, the density claims are immaterial until they prove yield at a technology node same as dram's today. There are multiple billions investment between 180nm and high yield (and low mask count) 2xnm, no matter how cool is the new memory technology. Second, speed claims must be explicitly about latency: flash bandwidth is as large as you want it, latency is ~100us (read). Even so, the moment anybody claims that latency is faster than Dram, you know they're feeding the hype and lying to you: dram latency does not depend on the memory technology, rather it depends on the array size. So an 8Gb chip of any memory technology that is fast enough, is likely to be just as fast as dram. Third: power consumption. Dram's active power is as low as it gets, the memory cell in particular stores information with really little energy. The array interconnect and circuitry consume most energy and a different memory technology won't change that.
- Symmetry 11y agoI think IBM found that the last level cache in their Power7 CPUs were faster with eDRAM than with SRAM because the reduction in transmission latency enabled by the smaller size made up for the higher cell latency so that's probably the crossover point where cell density wins over reasonable cell latencies. Of course memories with very large latency operations like a Flash erase can still dominate at much large sizes. And for off-die memory the transport is going to mask most differences anyways. The various sort of stacked memory coming into commercial use have the potential to reduce interconnect power and potentially make active RAM power at least slightly relevant. But I think the interesting thing about reducing RAM power consumption is decreasing passive power. Not that I expect anything to come of it for at least another half decade.
- russdill 11y agoActually you should be taking the claims very seriously. This has been an area Micron has been researching for decades. They've had a patent on the memory cell for about 11 years now (US6777705). Phase change memory has for a very long time been one of those just over the horizon technologies, but Micron has perfected it well enough to compete with NAND and partnered with Intel to bring it to market. This isn't something that appeared out of nowhere. Take a look at this presentation: https://www.micron.com/~/media/documents/products/presentation/gatwood_current_emerging_memory_landscape_fms2011_final.pdf https://www.micron.com/~/media/documents/products/presentati... Page 20 starts the section on "3-D Cross-Point Memory". They even have a 64Mb demonstrator on page 23, fabbed sometime before the 2011 Flash Memory Summit. Additional info on 64Mb demonstrator: http://investors.micron.com/releasedetail.cfm?releaseid=467247 http://investors.micron.com/releasedetail.cfm?releaseid=4672... Additionally, in early 2014, they stopped selling PCM modules, stating that "Micron's previous two generations of PCM process technologies are not available for new designs or technology evaluation, as the company is focused on developing a follow-on process to achieve lower cost per bit, lower power and higher performance." Job description details mentioning PCM, chalcogenides, and "cross point technology": https://www.linkedin.com/jobs2/view/12292797?trk=job_view_similar_jobs https://www.linkedin.com/jobs2/view/12292797?trk=job_view_si... And as far as process, as early as 2013 (2013 fall analyst conference handouts), Micron had PCM on a 45nm process and was listing 2xnm as next node. If they've gotten together with Intel and announced this, they have already reached 2xnm and/or beyond or are certain in their capability to do so. Because of the way flash memory is organized into pages and blocks, latency is very workload specific. Can you point out where anyone claimed it was better than DRAM latency?, the BBC article says "DRAM chips are still faster than 3D Xpoint, but the difference is much smaller than when compared with flash". And power consumption. This is PCM. Power consumption by the array when not being read/written is zero.
- rasz_pl 11y agoDear Micron, brace for a mother of all patent lawsuits from HP.
- wmf 11y agoHP certainly convinced the public that they have a monopoly on NVM. Too bad their technology isn't that successful.
- rasz_pl 11y agoHP itself is convinced they have a monopoly on the idea. Technology doesnt have to be successful if you have an army of lawyers working for you. Who wants to bet HP will sue just to keep Micron from shipping products for a couple of years.
- assface 11y ago> Dear Micron, brace for a mother of all patent lawsuits from HP. Ignore this person. They don't know what they are talking about. This is phase-change memory. It's been on everyone's radar for the last decade. HP is pushing their titanium oxide memristors. That's a completely different technology.
- throw1111 11y agoNo, apparently it's not PCM. >While they did not specifically state it, it looks to be phase change memory (edit at the Q&A Intel stated this is not Phase Change). Source: http://www.pcper.com/news/Storage/Breaking-Intel-and-Micron-announce-3D-XPoint-Technology-1000x-Faster-NAND http://www.pcper.com/news/Storage/Breaking-Intel-and-Micron-...
- kristianp 11y agoThis article is so thin on details. "3D XPoint works by changing the properties of the material that makes up its memory cells to either having a high resistance to electricity to represent a one or a low resistance to represent a zero." How does it do that?
- wmf 11y agoThe BBC isn't EE Times and they're never going to be. Also, Intel is going out of their way to avoid providing many details, so in this case it isn't the press who's dumbing it down.
- listic 11y agoLooks like this news item is made up from recent Intel's press release [1] and quite a bit of hand-waving. Take, for example, a claim that 'it would radically increase the number of people that could be supported for the same price'. We already have E7 series Xeons that support up to 1.5TB of RAM [2] (is it per socket? there can be up to 8 sockets per server) At that point, surely we would be constrained by processing and I/O, not RAM. [1] http://newsroom.intel.com/community/intel_newsroom/blog/2015/07/28/intel-and-micron-produce-breakthrough-memory-technology http://newsroom.intel.com/community/intel_newsroom/blog/2015... [2] http://ark.intel.com/products/84685/Intel-Xeon-Processor-E7-8890-v3-45M-Cache-2_50-GHz http://ark.intel.com/products/84685/Intel-Xeon-Processor-E7-...
- emmanueloga_ 11y ago"At that point in time, there was an 8:1 price/GB differential between the 512 GB SSDs and the 500 GB HDDs. On the smaller drives, the ratio was 4:1." [1] If anything I'm hoping the introduction of a competing new technology will make higher capacity SSDs cheaper. 1: http://www.zetta.net/blog/ssds-replace-hdds/ http://www.zetta.net/blog/ssds-replace-hdds/