2 ms·
I did it (while playing with reconfigurable dataflow CPUs), and timings (expectably) were awful.
by sklogic 12y ago
I did it (while playing with reconfigurable dataflow CPUs), and timings (expectably) were awful.
- sitkack 12y agoIt could see cases where there is an impedance mismatch between the guest FPGA running on the host FPGA. The idea of the genetic algorithm to map out the search space is to find some identity function HDL that allows for a clean 1:1 or 2:1 mapping of resources without incurring some combinatorial inefficiency. Maybe c-slowing could help with the timings, even if the area used was 4x it would still be a great research platform for reconfigurable computing since the bitstreams are proprietary, not documented and not portable. http://blog.notdot.net/2012/10/Build-your-own-FPGA http://blog.notdot.net/2012/10/Build-your-own-FPGA