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Berkeley’s RISC-V Wants to Be Free
- JoachimSchipper 12y agoDoes anyone have actual experience using RISC-V? It does come with a gcc toolchain, so it should just run C - but is it of any practical use yet, relative to the enormous ARM (or MIPS, or even SPARC) ecosystem?
- qwerta 12y agoWe were investigating CPUs for embedded use. I am not sure right now if it was RISC or MIPS. The performance was fraction of ARM or x86. But the consulting company would build SOC exactly to our spec. There were zero licensing fees. So for embedded use if performance is not important, I would seriously consider it.
- arbuge 12y agoReading the article, I see no reason why there should be any major performance issues inherent to RISC-V. Lack of an ecosystem looks like the issue, at least initially. But a $1m licensing fee for a CPU with an established ecosystem is an issue too...
- sspiff 12y agoThe reason the chips will be slower in practice is because they are produced in small batches, and need to be produced by smaller fabs and by extension much older process. MIPS is routinely produced at 95nm still.
- arbuge 12y agoMOSIS offers multi-project wafer (MPW) runs at 28nm from GlobalFoundries. https://www.mosis.com/products https://www.mosis.com/products
- asb 12y agoWe at lowRISC intend to produce in volume at 40nm or 28nm. http://www.lowrisc.org/ http://www.lowrisc.org/
- arbuge 12y agoLooks really interesting. Where are you guys based? Cambridge, UK I'm guessing?
- asb 12y agoYes, the core team is based in Cambridge, UK. However we do intend to be a truly open-source project, with an open and distributed development process which would involve arbitrarily geographically distributed third-party contributors.
- sspiff 12y agoThat's truly great to hear!
- alain94040 12y agoYes, and the fact that most of the performance comes from the micro-architecture. CPU design is all about the tradeoff between size, complexity, speed and power consumption. New RISC architectures tend to start on the low-end of the scale (clean architecture, short pipeline, small die), and if they are successful, move toward the x86/ugly/big/complex/fast spot.
- zhemao 12y agoIf you have a Xilinx FPGA, you can program our newly released Rocket core onto it and play around. https://github.com/ucb-bar/rocket-chip https://github.com/ucb-bar/rocket-chip We don't have a production-quality SoC out, so "practical use" is still a ways away.
- ash 12y agoIn your opinion, is it a good idea to replace ZPU with Rocket on Xilinx FPGA? What are advantages and disadvantages? http://opensource.zylin.com/zpu.htm http://opensource.zylin.com/zpu.htm
- zhemao 12y agoThe ZPU is designed to use as few FPGA resources as possible. So if you're looking for something to just do a little bit of control logic to tie things together, it probably is the way to go. Rocket on the other hand is a full-fledged in-order core with hardware mutliplier, single-precision and double-precision floating-point units, and MMU. Therefore, it can do things like boot a full Linux kernel, which the ZPU cannot. Rocket also has the RoCC co-processor interface, which allows you to define your own ISA extensions in Chisel.
- PythonicAlpha 12y agoAs much I heard, the ARM instruction set is also not so simple as it could. So a new, fresh and clean instruction set would be great and the comparison of the two architectures looks promising. I scan-read the paper, but did not encounter any number of registers. Does anybody know, how many registers this architecture has/supports ... is there any implementation yet? Hope, there will be an implementation soon, and maybe a smartphone or tablet computer based on it... (or a new Raspberry?) Edit: Now I see, should be 32 registers, based on the 32bit opcode-format (5 bits to address any register).
- sklogic 12y ago> Hope, there will be an implementation soon It's quite possible: http://www.lowrisc.org/ http://www.lowrisc.org/
- hga 12y agoPer that page, "multiple high performance [RISC-V] chips have been produced, at 45 and 28nm", which is very encouraging. More from the page, enough to get me interested: On performance: "As a rough guide we would expect ~500-1GHz at 40nm and ~1.0-1.5GHz at 28nm." Is volume fabrication feasible? Yes. There are a number of routes open to us. Early production runs are likely to be done in batches of ~25 wafers. This would yield around 100-200K good chips per batch. We expect to produce packaged chips for less than $10 each. Looking at this slide show: https://speakerdeck.com/asb/lowrisc-a-first-look https://speakerdeck.com/asb/lowrisc-a-first-look I see they're doing some very interesting things. Besides a lot of usual stuff, 2 cores each with I+D L1 and a shared L2 cache, they've added tags! 2 bits of tags, and they're thinking general purposes (e.g. GC) as well as security. That's big, something we haven't seen in hardware since Lisp Machines, to my knowledge. Also I/O "minions", non-coherent RISC-V cores, like the CDC 6600 etc. I'm now quite interested in the project.
- asb 12y agoThanks for your interest, we're hoping to share more very soon.
- higherpurpose 12y agoThis could be used for stuff like Arduino at least.
- zzzcpan 12y agoIs there a picture of RISC-V architecture (with pipeline, ALUs, FPUs)? Couldn't find anything.
- asb 12y agoYou're asking for a picture of a particular RISC-V implementation and its chosen microarchitecture. The RISC-V ISA has a range of different implementations each hitting different points in the design space and different trade-offs in terms of area/performance. See for instance the 'Sodor' teaching cores https://github.com/ucb-bar/riscv-sodor https://github.com/ucb-bar/riscv-sodor https://github.com/ucb-bar/riscv-sodor/wiki https://github.com/ucb-bar/riscv-sodor/wiki which demonstrate 1-stage, 2-stage, 3-stage, 5-stage, and micro-coded implementations.
- faragon 12y ago“There are two major products that came from Berkeley: LSD and Unix. We don't believe this to be a coincidence.” Unix came from Bell Labs in the East Coast. Californian Unix is just a non-elegant derivative, in my opinion (e.g. BSD sockets don't follow the "Unix philosophy", and one explanation could be the LSD, I agree with that).
- andolanra 12y agoFor that matter, LSD was first synthesized by Albert Hofmann while he was working in Basel, Switzerland.
- patrickg_zill 12y agoCould you maybe expand on your thoughts of BSD sockets vs. what SVR4 came up with?
- faragon 12y agoWell, BSD sockets don't use file abstraction. Plan 9 recovered "Unix philosophy" in that regard. In my opinion.
- bsder 12y agoWhy redesign a new core? We have plenty to choose from that have semi-existing ecosystems. First, I'd just go with a MIPS core. This is effectively the original RISC core, after all. Most patents have expired, and the Chinese have an implementation. If I didn't do that, I'd probably go with a DEC Alpha core. A shrunk, voltage optimized Alpha core was what drove the StrongARM series, and people raved about it. The Alpha architecture up through EV5 is quite clean. Given that most data suggests that ecosystem and optimization is more important than basic architecture, reinventing the wheel is not a good thing here.
- techdragon 12y agoUnfortunately the Alpha core is unlikely to ever return, much as its fans would like. Sparc is open back at the T1 T2 era pre oracle takeover. That's not a bad place to go, but MIPS is not really ideal due to a lot of factors that make the Chinese clones less than appealing.