3 ms·
ARM is using L3 cache as a DMA-like interconnect, on the SoC side of things.
by ganzuul 12y ago
ARM is using L3 cache as a DMA-like interconnect, on the SoC side of things.
- shortsightedsid 12y agoI'm not sure about ARMv8 but in ARMv7 SoCs the ARM Subsystem does not include L3. Plus each L1 is tied to each core.
- ganzuul 12y agoI believe this is a relevant source: http://www.arm.com/products/system-ip/interconnect/corelink-ccn-504-cache-coherent-network.php http://www.arm.com/products/system-ip/interconnect/corelink-... The L3 cache is 'integrated', which I presume means it's different names for the same thing.
- shortsightedsid 12y agoAh! Thanks for sharing. It is for ARMv8 which I really need to read up on.