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I've long wished of a middle ground between FPGAs and CPUs - namely a CPU with user-changable instructions. Have a CPU that is a CISC (but internally a microco
by TheLoneWolfling 12y ago
I've long wished of a middle ground between FPGAs and CPUs - namely a CPU with user-changable instructions.
Have a CPU that is a CISC (but internally a microcoded TTA), but with a large chunk of the microcode user-writable (So you have push-inst and pop-inst, where push-inst pushes the new instruction microcode into the microcode storage and copies the old instruction microcode onto the stack and pop-inst does the opposite). It keeps the advantages of fixed-width instructions while, depending on how the microcode is encoded, potentially having significant memory savings.
- sitkack 12y agoJITs could synth new instructions.
- rst 12y agoThe arc processor line from Synopsys does this commercially, I believe. Risc-v seems to be trying to support this sort of thing; there is reserved opcode space for implementation specific extensions
- TheLoneWolfling 12y agoI was under the impression that Synopsys' ARC processors were configurable at design time, not runtime. Or am I missing something? Have a link?