5 ms·

Can you say anything about where you are on the path towards silicon implementation or is it all still under wraps?

• willvarfar 12y ago
  We are working towards the FGPA. Its very early days, but the HW team is very experienced.
  • thesz 12y ago
    Wow. Finally. I've seen this Mill occdasionally pitching and always have been asking the same question: are your results from simulation or from FPGA? Now I know the answer. The most suspicious thing in Mill is that belt thing. To produce operands for N operations you need N*3 (2 for reads, one for write) ports of RAM. For even two operations that means 6 ports. No FPGA allow that out-of-the-box. Given that, you have to implement that in registers and logic, wasting FPGA resources. (AFAIK, silicon fabs also does not have such RAM blocks. you have to build them themselves, either from registers and logic (and make them slow) or using transistors (which make development process slow). this is THE source of relative slowness of Itanium and Elbrus thing from Russia.) If you want an advice, go for Tabula. You'll need many R/W ports per block of RAM, they seem to have those (12 ports RAM blocks). Maybe your design won't be as slow as I think it will.
    • Rusky 12y ago
      If I understand correctly from what they've said so far, there is no RAM/register file with N*3 ports, it just reuses the outputs of the functional units. That's also nowhere near the source of slowness in the Itanium.
      • thesz 12y ago
        Okay. The reuse of output from functional units was done in TTA CPUs (Transport Triggered Architectures). Guess how they fare if you probable never heard of them? Guess also how fast or slow they are compared to regular OOO CPUs. You will be right if you guess that they are not that good in terms of raw performance and they are not that fast in terms of operating frequency. They are not fast in either way precisely because they use crossbar as a operand delivery network. They also can have FIFOs as the switching network or as an another functional unit dedicated to spreading information, but most often it is not used.
    • marcosdumay 12y ago
      You don't put a RAM block in the CPU pipeline. RAM is much slower, thus you keep is several subsystems away.
      • cfallin 12y ago
        "RAM" here means SRAM (static RAM). That just means "array of storage elements (latches) connected by bitlines and wordlines", which is way more efficient than "random latches we scattered throughout the chip". SRAMs are used extensively for indexed storage such as physical register files, queues, predictor arrays, etc in modern microarchitectures.
        • marcosdumay 12y ago
          Anyway, unless you have a very small array, even addressing is enough to make it slow. And arrays were already big at the time I programmed FPGAs, I can only imagine they are much larger now.
    • pjc50 12y ago
      you need N3 (2 for reads, one for write) ports of RAM What? This isn't the 1980s, that's not how you register file. Realistically a "register" these days is an abstract concept, a label attached to a value somewhere in the pipeline. It's the job of instruction decode to keep track of exactly where to load it from.
      • cfallin 12y ago
        Yes, renaming exists in modern cores, but where do you think the physical values are stored? Answer: there's still a "physical register file". The renamer maps logical register slots to PRF entries. This is well-covered in academic comparch literature from the 90s onward (and is how it's done in real modern OoO cores too, see e.g. articles on Intel Sandy Bridge). (disclaimer: I'm rebutting the general point about microarchitectures and register files/SRAMs, but haven't studied the Mill in any depth...)
    • igodard 12y ago
      If you watch the Belt talk on our site, and know how a modern OOO machine works on the inside, then you will recognize that the Belt is a forwarding network, sometimes also called a bypass. There is no RAM, "S" or otherwise, no general registers, and no ports. Bypasses are nothing new; what is novel is how we are able to handle triple the number of data paths than other machines, the fact that the bypass is exposed to the program rather than being hidden behind the register metaphor, and that the program model is a single-assignment FIFO. See those talks for more. There is no better way to speed up registers and SRAM than by having none at all.
      • hahainternet 12y ago
        Thanks for commenting Ivan. I'm excited for the future and hope to see more material produced by you. The original belt video absolutely blew my mind and I feel that Mill has the opportunity to really revolutionise the entire industry.
      • thesz 12y ago
        Okay. Your model looks like TTA - a machine that is built on bypasses. They are not new and they can be used to create very efficient chips (in terms of operations/watt) for some fixed functions (precisely, FFT of 2^N). But they are 1) not fast in terms of raw performance for general purpose tasks, 2) not fast in terms of operating frequency and most important 3) prone to stall when present with non-deterministic delays like access to RAM. You can add whatever functional units you like to TTA design, including content-addressable memory in disguise as FIFO. TTA design with such device will be identical to what you've described above. I won't think you will improve performance very much with this trick. PS "not fast for general purpose tasks" - in some benchmarks TTA architectures executed gcc 10+ times slower than general purpose CPU with same frequency. "not fast in operating frequency" - TTA requires crossbar, which is slow in 2D. You cannot make it fast. "prone to stall" - you have to stop complete pipeline for a cache miss, otherwise you'll have divergence in execution.