7 ms·

I have yet to go through this talk but I have been waiting for this for a while. Mill is possibly the most interesting thing in all of computing right now.

nraynaud 12y ago
I really feel like a brainless fanboy too, I'm watching everything about this company. Not being an expert in CPU design, I know I lack the knowledge to criticize what I see, I'm just slurping marketing material straight from the bullshit hose, but I can't help myself, I love it.
- hahainternet 12y ago
  One of the things about Mill that feels reassuring is that the information is being presented slowly, step by step to people who have good reason to give a shit. If it was purely marketing, they'd have a kickstarter up and be promising performance figures without a billion caveats.
  - XorNot 12y ago
    Hate to say it, but there's nothing new under the sun when it comes to marketing. Everyone tries everything and modifies based on how well it works. A lot of slow information is the same as trying to go for the quick money. At the end of the day, the problem with the Mill is there's no hardware implemented. No real world benchmarks to be had, and the world of hardware design is full of seemingly slamdunk ideas which have giant problems in actual implementation. This isn't to disparage the Mill or its team - but the content and results are important. Not the style of the message. Anyone can style a message.
RyanMiller 12y ago
I see this posted every time Mill gets linked. Could someone simply explain the significance of the Mill architecture?
- willvarfar 12y ago
  (Mill team, so biased; thanks for the chance to pitch ;) We are a DSP that can run general purpose code. Traditionally, to run general purpose code fast you needed an out-of-order superscalar architecture, as all the x86 and RISC cores are these days. DSPs have substantially better performance and substantially better efficiency, but have traditionally been ineffective executing general purpose code (such as the web browser you are using to read this). The Mill is a synergy of lots of small breakthroughs that together deliver significant improvements to general purpose single threaded code. Its been held that cores have stopped getting faster. We're faster. And we have similar as yet not filed improvements for multicore too.
  - rrmm 12y ago
    Can you say anything about where you are on the path towards silicon implementation or is it all still under wraps?
    - willvarfar 12y ago
      We are working towards the FGPA. Its very early days, but the HW team is very experienced.
      - thesz 12y ago
        Wow. Finally. I've seen this Mill occdasionally pitching and always have been asking the same question: are your results from simulation or from FPGA? Now I know the answer. The most suspicious thing in Mill is that belt thing. To produce operands for N operations you need N*3 (2 for reads, one for write) ports of RAM. For even two operations that means 6 ports. No FPGA allow that out-of-the-box. Given that, you have to implement that in registers and logic, wasting FPGA resources. (AFAIK, silicon fabs also does not have such RAM blocks. you have to build them themselves, either from registers and logic (and make them slow) or using transistors (which make development process slow). this is THE source of relative slowness of Itanium and Elbrus thing from Russia.) If you want an advice, go for Tabula. You'll need many R/W ports per block of RAM, they seem to have those (12 ports RAM blocks). Maybe your design won't be as slow as I think it will.

nraynaud 12y ago

I really feel like a brainless fanboy too, I'm watching everything about this company. Not being an expert in CPU design, I know I lack the knowledge to criticize what I see, I'm just slurping marketing material straight from the bullshit hose, but I can't help myself, I love it.

hahainternet 12y ago
One of the things about Mill that feels reassuring is that the information is being presented slowly, step by step to people who have good reason to give a shit. If it was purely marketing, they'd have a kickstarter up and be promising performance figures without a billion caveats.
- XorNot 12y ago
  Hate to say it, but there's nothing new under the sun when it comes to marketing. Everyone tries everything and modifies based on how well it works. A lot of slow information is the same as trying to go for the quick money. At the end of the day, the problem with the Mill is there's no hardware implemented. No real world benchmarks to be had, and the world of hardware design is full of seemingly slamdunk ideas which have giant problems in actual implementation. This isn't to disparage the Mill or its team - but the content and results are important. Not the style of the message. Anyone can style a message.

RyanMiller 12y ago

I see this posted every time Mill gets linked. Could someone simply explain the significance of the Mill architecture?

willvarfar 12y ago
(Mill team, so biased; thanks for the chance to pitch ;) We are a DSP that can run general purpose code. Traditionally, to run general purpose code fast you needed an out-of-order superscalar architecture, as all the x86 and RISC cores are these days. DSPs have substantially better performance and substantially better efficiency, but have traditionally been ineffective executing general purpose code (such as the web browser you are using to read this). The Mill is a synergy of lots of small breakthroughs that together deliver significant improvements to general purpose single threaded code. Its been held that cores have stopped getting faster. We're faster. And we have similar as yet not filed improvements for multicore too.
- rrmm 12y ago
  Can you say anything about where you are on the path towards silicon implementation or is it all still under wraps?
  - willvarfar 12y ago
    We are working towards the FGPA. Its very early days, but the HW team is very experienced.
    - thesz 12y ago
      Wow. Finally. I've seen this Mill occdasionally pitching and always have been asking the same question: are your results from simulation or from FPGA? Now I know the answer. The most suspicious thing in Mill is that belt thing. To produce operands for N operations you need N*3 (2 for reads, one for write) ports of RAM. For even two operations that means 6 ports. No FPGA allow that out-of-the-box. Given that, you have to implement that in registers and logic, wasting FPGA resources. (AFAIK, silicon fabs also does not have such RAM blocks. you have to build them themselves, either from registers and logic (and make them slow) or using transistors (which make development process slow). this is THE source of relative slowness of Itanium and Elbrus thing from Russia.) If you want an advice, go for Tabula. You'll need many R/W ports per block of RAM, they seem to have those (12 ports RAM blocks). Maybe your design won't be as slow as I think it will.