7 ms·
If you haven't heard of Parallella before (like me) and want to learn more: http://www.parallella.org/ http://www.parallella.org/ Edit: Ok, here's my quick sum
by awda 12y ago
If you haven't heard of Parallella before (like me) and want to learn more: http://www.parallella.org/ http://www.parallella.org/
Edit:
Ok, here's my quick summary. Please correct me if I'm wrong:
This looks like a small PCB (raspberrypi-alike) that sits the main attraction: a 16- or 64-core Epiphany coprocessor, as well as an ARM cpu to run the OS. Not sure how these relate in performance to other coprocessors (GPUs with OpenCL?). Power draw seems low (5W). Would love to read more about the architecture, why Epiphany processors are special, etc.
- mintplant 12y agoMore info about Epiphany and its architecture can be found on Adapteeva's Wikipedia page [1]. [1] http://en.wikipedia.org/wiki/Adapteva#Products http://en.wikipedia.org/wiki/Adapteva#Products
- vidarh 12y agoIt's a dual ARM core Zynq SoC + the Epiphany. The Zynq has an on-die FPGA. Part of the FPGA is used for "glue" for the Epiphany, but you can update the FPGA config as well, with some care. The main CPU is substantially faster than the Pi, but it doesn't have HW accelerated graphics, so it's not a speed daemon for desktop/workstation type use. As for the Epiphany, assume that it'll be slower than most GPU's for tasks that GPU's are good for. That is, if you can make do with few instruction streams, the Epiphany is not well suited for it, as most GPUs will blow the current chips out of the water in terms of performance. If, on the other hand, your problem is poorly suited for GPUs due to lots of independent instruction streams, it may be better suited. One of the most interesting aspects of the Epiphany is that is can also be connected into a grid - each chip has four high speed links that can be connected to other Epiphany chips, or be used to interface with the main CPU or off-chip memory. The cores can all access each-others memory without any special instructions, including that of the cores on other Epiphany chips that are hooked up via the external links - the only difference between in-core and out-of-core memory access is the speed.
- MichaelGG 12y agoIf you set up a grid, how is cache coherency handled and what's the impact on performance?
- watmough 12y agoI'd imagine it works like a Transputer, and the only accessible memory is local to the chip, with communications including data coming down the serial links.
- vidarh 12y agoThe chips have a flat address space that covers any Epiphany chips that have been interconnected via the serial links, and the main memory of the CPU. You can address core-local memory, memory in another core, or main memory the same way - the difference is speed. There's no cache, and you're responsible for avoiding race conditions in memory access yourself.
- vidarh 12y agoThe Epiphany cores have no cache. EDIT: And if you want to read/write the same memory areas from multiple cores, it's your own responsibility to either get the timing right, or use other means (e.g. you can trigger interrupts in another core) to signal when it is safe for another core to access data.
- sitkack 12y agoI am waiting in anticipation for all the excellent blog posts about running Haskell on the Ephiphany cores.
- chroem 12y agoDo the epiphany cores have storage and network I/O access, or are they something more similar to a GPU? In other words, could I write an epiphany webserver?
- wtracy 12y ago
- aaron695 12y agoKickstarter page is also a good round up https://www.kickstarter.com/projects/adapteva/parallella-a-supercomputer-for-everyone https://www.kickstarter.com/projects/adapteva/parallella-a-s...