6 ms·
Micron Automata Processor – A Brief Introduction
- erikj 13y agoHere's more: http://www.micron.com/~/media/Documents/Products/Other%20Documents/automata_processing_technical_paper.pdf http://www.micron.com/~/media/Documents/Products/Other%20Doc...
- greglindahl 13y agoGood: a memory vendor finally getting serious about "processor in memory" silicon. Bad: Doesn't mention all the research that was done on these sorts of things already. I mean, it makes a great story that you invented the whole thing from scratch, but nothing screams "this is a slick marketing doc" more than pretending that sort of thing. Or maybe they did ignore the literature and made a bunch of mistakes as a result? Edit: wow, the scientific paper does the same thing.
- crb002 13y agoWhat are some of the good papers?
- greglindahl 13y agoPIMs are outside my field, but Wikipedia looks like a reasonable start (http://en.wikipedia.org/wiki/Processor-in-memory http://en.wikipedia.org/wiki/Processor-in-memory).
- Someone 13y agoI don't have a better one handy, but this definitely is a Wikipedia entry where "This article needs additional citations for verification." is more than true. For example: "In the 1980s, a tiny CPU that executed FORTH was fabricated into a DRAM chip to improve PUSH and POP. FORTH is a Stack-oriented programming language and this improved its efficiency." I would love to see a reference there. Anybody know one? If it only had pop and push, I wouldn't call it a processor in memory. I wouldn't say the MuP21 (http://www.ultratechnology.com/p21.html#p21 http://www.ultratechnology.com/p21.html#p21) or F21 (http://www.ultratechnology.com/f21cpu.html http://www.ultratechnology.com/f21cpu.html) had a processor in memory, either. Aside: I Googled for this (mythical?) CPU and did not find it, but I did find the next hot thing in agile programming: "Initially OKAD was implemented as the only application program in OK and was an experiment in sourceless programming. The structure of the programs looks like Forth code, but there was no Forth compiler or interpreter except Chuck himself. He entered the kernel of OK using a debugger and built the tools he need to build the rest of OK and OKAD" (http://www.ultratechnology.com/okad.htm http://www.ultratechnology.com/okad.htm) Somebody should start a project where your system runs compiled Forth code, and the only way to backup the system is through a command that retrieve a set of functions from another running system ("please replace the 'BEEP' function with the one on the system at this IP address")
- mud_dauber 13y agoHarris Semiconductor attempted to intro the "RTX" microncontroller in the late 1980s. It featured a true Forth-based instruction set. RTX never caught traction due (IMO) to the lack of developer tools; the group was discontinued in ~1989.
- Someone 13y agoIf you mean http://en.wikipedia.org/wiki/RTX2010 http://en.wikipedia.org/wiki/RTX2010, that's nothing like what this describes. It's just a CPU with two hardware stacks (one more than the 6502 had). There's plenty of alternatives for Forth hardware, especially if you are willing to use a FOGA. What this describes is more like Moore's GreenArray hardware, but with way more, less powerful chips (if it were DRAM-like, a major difference would be that you would be able to address all those CPUs from the outside, not just a few, like in the GreenArray chips)
- troymc 13y agoIf you do a search for "Cellular Automata Machines" on Google Scholar, you'll have a good start. The idea of cellular automata was first developed by von Neumann and his colleagues back in the 1940s.
- darkmighty 13y agoDo you know what's being talked about here? It's state machines (http://en.wikipedia.org/wiki/Deterministic_finite_automaton http://en.wikipedia.org/wiki/Deterministic_finite_automaton), not cellular automata
- marcosdumay 13y agoCellular automata is what you get when you use automata as cells in a network. Just like at the presentation.
- wsxcde 13y agoThis (http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=375174 http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumb...) is one of the classic papers on PIMs.
- crb002 13y agoYou should reach out to the IPDPS 2014 program committee and see this reference gets added.
- eloff 13y agoI hope the refs reject it. That's unacceptable to have a paper that was written by a marketing department. There's nothing new or original about FPGAs. They make it sound like they invented the concept. They may have improved on it, but they didn't talk about the specifics of that.
- crb002 13y agoThey already got one accepted to IPDPS 2014, "Finding Motifs in Biological Sequences Using the Micron Automata Processor" http://www.ipdps.org/ipdps2014/2014_%20advance_program.html http://www.ipdps.org/ipdps2014/2014_%20advance_program.html
- TrainedMonkey 13y agoI had a professor mention concept like this during microprocessor class. Basically idea comes from efficient organization of CPU cache. Using LRU queue, instead of having 4 way associative cache with each memory location tied to a specific spot in one of those 4 banks. Issue with LRU queue is that you would need to search all memory tag locations to determine if any of them store correct address. That is a boatload of transistors to accomplish it within latencies demanded of CPU cache, so we have cache with only 4 [1] locations to search for each memory address. It looks like micron figured out a way to place some logic close to memory chips to search entire memory for matching pattern. Would be interesting to know how they did it. [1] Number of locations to search depends on associativity of the cache. I used 4 way associative cache in my example.
- p1esk 13y agoWith a regular 4-way associative cache you search 4 tags to find the right block. With fully associative cache, you search all tags (where a tag would mean an entire block number), and it is typically implemented with CAM, where "some logic [is placed] close to memory chips to search entire memory for matching pattern". Is that what you're describing? Are you saying Micron invented some form of CAM?
- TrainedMonkey 13y agoThat is the gist I got from the presentation. http://en.wikipedia.org/wiki/Content-addressable_memory http://en.wikipedia.org/wiki/Content-addressable_memory
- marcosdumay 13y ago> Good: a memory vendor finally getting serious about "processor in memory" silicon. Let's face it, Moore's Law is dead. Now we must extract the sub-exponential gains that come from architecture optimizations, and Non-uniform memory can lead to huge ones. It's time to finally take the challenge of programming such exotic kinds of computers. The good news is that now our computers are good enough to help us.
- p1esk 13y ago> Moore's Law is dead. What makes you say that? Intel would certainly disagree...
- DougMerritt 13y agoThe particular form of Moore's Law that used to give regular doublings of clock speed is the one that has been dead for years. Although not the original formulation (which was number of transistors), the clock speed one is very significant because it means that sequential computations are no longer getting faster exponentially. The forms of Moore's Law that remain are still being used advantageously by Intel, e.g. for more cores amongst lots of other things, but it's not helping as much, since not all computations can be parallelized.
- p1esk 13y agoThere's only one formulation of Moore's Law - the one from 1965 paper. Clock speed has nothing to do with it. Clock speed is generally not a good indicator of a processor performance. I'm guessing a single 2GHz Haswell core is faster than 4GHz P4, due to a number of significant architectural improvements, which were made possible by the larger number of transistors available. Keep in mind that processor performance per watt continues to improve significantly every two years, with no sign of slowing down in the nearest future.
- DougMerritt 13y ago> There's only one formulation of Moore's Law You can't dictate that to the world: http://en.wikipedia.org/wiki/Moore's_law#Other_formulations_and_similar_laws http://en.wikipedia.org/wiki/Moore's_law#Other_formulations_... > Clock speed is generally not a good indicator of a processor performance. I didn't say it was. But if all else is equal, the exact same architecture running at a doubled clock frequency will run exactly twice as fast as the original. You are arguing that not all else is usually equal, and although true, it's a different topic. The point is that the "free" doubling of speed that we used to get stopped some years back. Computation per watt is another important subject -- but it is s a different topic (and for that matter, is yet another formulation of Moore's Law). There are a thousand issues that are important to varying degrees when discussing architecture and performance, but there is no point acting like we don't know what people mean when they say "Moore's Law has failed". What they mean is quite clear.
- bamakhrama 13y agoThe slides are misleading. "Memory Wall" refers to the fact that CPU speed has been doubling every 24 months from 1960s till early 2000s (annual improvement rate is 50%), while RAM memory speed doubles every 10 years (annual improvement rate is 10%). This "memory wall" is there regardless of the processor architecture that you use.
- wlesieutre 13y agoMath nitpick: It's a bit more complicated than that with exponential growth. You can't divide up 100% over 10 years and say it was 10% each year, instead you have to solve 2=1.1^x, and find that it doubles in 7.27 years. If something grows 10% a year for 10 years, it actually ends up at 2.59x its original size.
- greglindahl 13y agoRule of 72: doubles in 10 years, annual %age is 72/10 = 7.2%. Close to the right answer, easy to do in your head. http://en.wikipedia.org/wiki/Rule_of_72 http://en.wikipedia.org/wiki/Rule_of_72
- wlesieutre 13y agoHuh, that's a handy approximation. I'd never heard of it before.
- majke 13y ago> "Deep packet inspection to monetize traffic" Whoops.
- smoyer 13y agoExcuse me! ... I'm with the NSA and we really need to monetize some traffic. Have you seen our budget?
- agumonkey 13y agoSo this is like going from SMTP to IMAP ?
- smoyer 13y agoI didn't down-vote you, but if you were serious I think you should find a profession outside of technology.
- agumonkey 13y agoI was almost serious, skimming through the diagram gave me the impression they were moving computation capabilities close to the data ~backend.
- smoyer 13y agoOh ... I completely missed that interpretation (maybe I'm too close to these techniques). In any case, it's probably better to think of the system as a giant state machine in which the data are states and the operations are transitions. Its processing and memory co-mingled. You'll notice that it's got a very wide data width (not a new idea) that speeds it up tremendously for parallizeable tasks, but it's actually slowing down the "clock" since the memory itself is still the slowest part. (I also upvoted you ... you shouldn't get penalized for an honest question)
- dclara 13y agoUpvoted you. We need more insights like this than the document itself. The concept of state machine, PIM (processing in memory) and parallelization is the core, looks like Micro has some implementation now. That's why they call it an Automata Processor (AP).
- dandelany 13y agoWhat a rude, condescending thing to say to someone who is asking for help understanding something.
- wmf 13y agoThe NSA processor—now available commercially!
- ars 13y agoSo, when can I get one and start mining bitcoins? Or since it's all about memory, litecoins?
- eloff 13y agoWith bitcoin we passed the FPGA mark a while ago, now it's all about custom ASIC chips.
- ChuckMcM 13y agoMicron demonstrated early versions of this at Microprocessor Forum in 2004 or 2005. So it isn't exactly "new" but being able to actually get one is. Pattern algorithms are pretty difficult to synthesize however, see the Conway Glider search as an example. One of the challenges is that the set of 'instructions' and the solution possibilities are quite tightly interlinked. I hope that I can get my hands on one at some point, some of the old texture research from the Image Processing Institute would really fly on this thing.
- rasz_pl 13y agoCant wait for Stephen Wolfram to claim it his own invention.
- windexh8er 13y agoI think there's more here than most comments reflect - yes, this is being done in many implementations today, but not nearly as efficiently. 4W for 1Gb of DFA stream analysis? That's pretty crazy considering that can put full on content inspection in a SOHO device that can end up in consumers networks. DFA is the shift from file based scanning in network security and offers parallelism efficiencies far beyond most of the UTM type platforms out there today. There are only a few companies using stream based platforms (Palo Alto Networks is one) and this is why the platform can do much more content scanning in one pass vs the legacy devices. But, this is killer for SOHO networking IMHO. Puts a ton of power into the next wave of network security.
- dkural 13y agoThe bioinformatics slides in that presentation make no sense. The image shown doesn't map in any way to the bullet points.