5 ms·
xor rax,rax I used this construct often to zero a register, in the time that memory and CPU cycles were scarce. But nowadays, my time is a more valuable resour
by Luyt 13y ago
xor rax,rax
I used this construct often to zero a register, in the time that memory and CPU cycles were scarce. But nowadays, my time is a more valuable resource, and I tend to write:
mov rax, 0
It takes a somewhat longer instruction code, and a few CPU cycles more, but it conveys meaning better.
- sneak 13y ago> It takes a somewhat longer instruction code, and a few CPU cycles more, but it conveys meaning better. So do webservers written in Python. I don't think that was the point of this project.
- XorNot 13y agoCouldn't you just find-replace this in a makefile? Then again almost everything about assembly gets a bit "isn't that what we made other languages for?"
- xyzzy123 13y agoPersonally I find the xor form easier to follow, it's SUCH a long-standing convention that if I saw a mov rax, 0 I would wonder what was going on.
- rjzzleep 13y agosame here. _but_ if you weren't proficient in writing and reading asm the statement would no longer be true. now, you could argue if that were that the case, wth is that person doing there anyway. also if you compile something like `return 0;` it used to be compiled down to `xor eax,eax; ret;`, but meh barely anyone i know coding these days even knew this to begin with.
- lttlrck 13y agoA few more instruction cycles? Which architecture and which decade?
- ksk 13y agoThis decade :) For modern out-of-order CPUs - xor reg1,reg2 is problematic because the result depends on the previous contents of the register. Hence it cannot be executed out of order. However as a special case xor reg1,reg1 (along with sub reg1,reg1) will be detected by the cpu (intel anyway) as a 'zero idiom' instruction and because it has a smaller opcode than mov reg,0 its preferred. There are also other complex reasons - for detailed info see 3.5.1.8 in the Intel optimization manual.
- Dylan16807 13y ago>This decade :) The initial claim was that mov reg,0 was slower to execute.
- teraflop 13y agoSmaller opcodes will, all else being equal, take up fewer instruction decide cycles and less space in the CPU cache.
- ksk 13y agoA CPU cycle is Fetch,Decode,Execute,Writeback. The 'zero idiom' instructions do not consume any 'Execute' resources. Apart from this.. as the other poster said, smaller opcodes means more instructions can fit inside the caches.
- csmithuk 13y agoxoring something with itself is a common idiom in ASM. Been doing it since the Z80 (XOR A). Not sure that meaning is enhanced at all.