3 ms·

I wonder how much more successful FPGAs would be if you could actually write your own compilers for them. As of now, as far as I can tell, none of the major FP

by lambda 13y ago

I wonder how much more successful FPGAs would be if you could actually write your own compilers for them. As of now, as far as I can tell, none of the major FPGA vendors actually document the actual format of their programming. You have to use a compiler from them to compile a netlist down to the raw bytecode that's actually sent to the FPGA to program it. This means that there are many potential uses of an FPGA that you just can't do. For instance, you can't write a GLSL shader compiler that compiles down to an FPGA on the fly, or compile OpenCL to an FPGA, or add a language extension that compiles certain highly parallelizable statements in your language down to an FPGA. It seems that FPGA manufacturers are missing out on an awful lot by not actually opening up their hardware to experimentation by third parties. Anyone know why exactly they act this way?

jwise0 13y ago
You can write the tools you describe on top of any existing tool stack -- you'll just have to use the hardware description language as an IL. (Indeed, many tools already do this.) You could write your own synthesis front-end and place-and-route back-end, but they're not like any compilers you've ever seen before. (A recent Coursera class [1] went into pretty good detail about how synthesis and place and route work.) I think that the unfamiliarity is probably why there are no Open Source toolchains for it. For Virtex-II platform, Xilinx provided a tool to edit bitfiles, called JBits [2], but it seems to be well and truly dead[3]. [1] https://www.coursera.org/course/vlsicad https://www.coursera.org/course/vlsicad [2] http://www.xilinx.com/labs/projects/jbits/ http://www.xilinx.com/labs/projects/jbits/ [3] http://forums.xilinx.com/t5/Virtex-Family-FPGAs/Question-about-JBits/td-p/33215 http://forums.xilinx.com/t5/Virtex-Family-FPGAs/Question-abo...
- lambda 13y ago
  Sure, you could use tools that target the HDL as an IL, if you wanted to write that code yourself and then ship it to your customers as a binary blob, as their HDL compilers need to be specifically licensed, and aren't, as far as I know, something designed to be used as a back-end component in shipping software. But that limits its usefulness for something like, say, writing a GLSL compiler so you can use your FPGA as a GPU, and are then able to run arbitrary GLSL code on it. I agree that it's definitely a much different than writing a compiler backend for a CPU. You are definitely going to have different abstractions that will apply well to it. But that's fine; that's what I'm interested in, writing a compiler for a very different kind of platform. The problem is, as far as I can tell, they don't document their actual bitstream format, so you must use their licensed tools any time you actually want to compile something new for the FPGA. And that precludes a lot of use cases.
unwind 13y ago
> [...] you can't [...] or compile OpenCL to an FPGA I noticed that Altera's own product page (http://www.altera.com/devices/fpga/stratix-fpgas/stratix10/stx10-index.jsp http://www.altera.com/devices/fpga/stratix-fpgas/stratix10/s...) specifically mentions that: > C-based design entry using the Altera SDK for OpenCL, offering a design environment that is easy to implement on FPGAs But it seems the release is very early, I was not able to find pricing or even packaging information. It does seem to pack quite a punch, from the performance numbers on the above page ("56 Gbps chip-to-chip/module capability for leading edge interface standards" sounds like ... a lot). Also, that page has some super-annoying trickery that appends text when you copy and paste, to insert a link back to some Altera page. What idiocy.
- lambda 13y ago
  So, Altera is able to write an OpenCL compiler for their platform. I am not, because they don't document the low-level bitstream format; you always need to have some licensed Altera compiler in between what you write and the actual hardware.

by lambda 13y ago

jwise0 13y ago

You can write the tools you describe on top of any existing tool stack -- you'll just have to use the hardware description language as an IL. (Indeed, many tools already do this.) You could write your own synthesis front-end and place-and-route back-end, but they're not like any compilers you've ever seen before. (A recent Coursera class [1] went into pretty good detail about how synthesis and place and route work.) I think that the unfamiliarity is probably why there are no Open Source toolchains for it. For Virtex-II platform, Xilinx provided a tool to edit bitfiles, called JBits [2], but it seems to be well and truly dead[3]. [1] https://www.coursera.org/course/vlsicad https://www.coursera.org/course/vlsicad [2] http://www.xilinx.com/labs/projects/jbits/ http://www.xilinx.com/labs/projects/jbits/ [3] http://forums.xilinx.com/t5/Virtex-Family-FPGAs/Question-about-JBits/td-p/33215 http://forums.xilinx.com/t5/Virtex-Family-FPGAs/Question-abo...

lambda 13y ago
Sure, you could use tools that target the HDL as an IL, if you wanted to write that code yourself and then ship it to your customers as a binary blob, as their HDL compilers need to be specifically licensed, and aren't, as far as I know, something designed to be used as a back-end component in shipping software. But that limits its usefulness for something like, say, writing a GLSL compiler so you can use your FPGA as a GPU, and are then able to run arbitrary GLSL code on it. I agree that it's definitely a much different than writing a compiler backend for a CPU. You are definitely going to have different abstractions that will apply well to it. But that's fine; that's what I'm interested in, writing a compiler for a very different kind of platform. The problem is, as far as I can tell, they don't document their actual bitstream format, so you must use their licensed tools any time you actually want to compile something new for the FPGA. And that precludes a lot of use cases.

unwind 13y ago

> [...] you can't [...] or compile OpenCL to an FPGA I noticed that Altera's own product page (http://www.altera.com/devices/fpga/stratix-fpgas/stratix10/stx10-index.jsp http://www.altera.com/devices/fpga/stratix-fpgas/stratix10/s...) specifically mentions that: > C-based design entry using the Altera SDK for OpenCL, offering a design environment that is easy to implement on FPGAs But it seems the release is very early, I was not able to find pricing or even packaging information. It does seem to pack quite a punch, from the performance numbers on the above page ("56 Gbps chip-to-chip/module capability for leading edge interface standards" sounds like ... a lot). Also, that page has some super-annoying trickery that appends text when you copy and paste, to insert a link back to some Altera page. What idiocy.

lambda 13y ago
So, Altera is able to write an OpenCL compiler for their platform. I am not, because they don't document the low-level bitstream format; you always need to have some licensed Altera compiler in between what you write and the actual hardware.