Yup, four cores. No crazy muxing needed because only one kind is ever active at a time and the other kind kept in reset, so there's no need to do any runtime ar

Yup, four cores. No crazy muxing needed because only one kind is ever active at a time and the other kind kept in reset, so there's no need to do any runtime arbitration - basically just a dumb switch on few dozen signals. The bonus RISC-V cores take up basically zero additional die space: for the RP2350 the lower size bound is the space needed at the periphery for connections to the outside world, and (unlike something like SRAM and analog IP blocks) logic is not too difficult to rearrange or even compress. This is the kind of thing that tends to start as an engineer joking about having enough spare space to fit in their toy RISC-V core, and then actually doing it. Run out of space during development? Just delete it, it's only an unexpected bonus feature after all. It causes issues during testing? Permanently fuse it off and nobody will notice it was ever there. High-end chips are filled with dozens of "chicken bits" to gate off functionality they might not be able to get to work properly, so in a small company like Raspberry Pi it probably wouldn't be too hard to convince management to take the tiny additional risk in return for a significant PR possibility.