3 ms·

The RP2350 is Raspberry Pi’s dual-core microcontroller: each processor socket can select either an Arm Cortex-M33 or a RISC-V Hazard3 core at boot. Does that m

The RP2350 is Raspberry Pi’s dual-core microcontroller: each processor socket can select either an Arm Cortex-M33 or a RISC-V Hazard3 core at boot. Does that mean there are four cores on the die? Is there crazy amounts of MUXing going on? Does the extra, semi-unused area give the chip a premium price tag? Or did I misinterpret this?

raphlinus 7d ago
Yes, four cores in the chip. And yes, there's additional muxing, but I think that adds a fairly small amount of chip area compared with the crossbar. In addition to the two core slots, there are a lot of peripherals contending for single cycle bus access.
LukeShu 7d ago
> a premium price tag? $0.80 in bulk. Around $1.25 for individual quantities, depending on who your reseller is. AIUI, the CPU cores are a small fraction of the die area compared to all the peripherals on the chip.
crote 7d ago
Yup, four cores. No crazy muxing needed because only one kind is ever active at a time and the other kind kept in reset, so there's no need to do any runtime arbitration - basically just a dumb switch on few dozen signals. The bonus RISC-V cores take up basically zero additional die space: for the RP2350 the lower size bound is the space needed at the periphery for connections to the outside world, and (unlike something like SRAM and analog IP blocks) logic is not too difficult to rearrange or even compress. This is the kind of thing that tends to start as an engineer joking about having enough spare space to fit in their toy RISC-V core, and then actually doing it. Run out of space during development? Just delete it, it's only an unexpected bonus feature after all. It causes issues during testing? Permanently fuse it off and nobody will notice it was ever there. High-end chips are filled with dozens of "chicken bits" to gate off functionality they might not be able to get to work properly, so in a small company like Raspberry Pi it probably wouldn't be too hard to convince management to take the tiny additional risk in return for a significant PR possibility.

raphlinus 7d ago

Yes, four cores in the chip. And yes, there's additional muxing, but I think that adds a fairly small amount of chip area compared with the crossbar. In addition to the two core slots, there are a lot of peripherals contending for single cycle bus access.

LukeShu 7d ago

> a premium price tag? $0.80 in bulk. Around $1.25 for individual quantities, depending on who your reseller is. AIUI, the CPU cores are a small fraction of the die area compared to all the peripherals on the chip.

crote 7d ago

Yup, four cores. No crazy muxing needed because only one kind is ever active at a time and the other kind kept in reset, so there's no need to do any runtime arbitration - basically just a dumb switch on few dozen signals. The bonus RISC-V cores take up basically zero additional die space: for the RP2350 the lower size bound is the space needed at the periphery for connections to the outside world, and (unlike something like SRAM and analog IP blocks) logic is not too difficult to rearrange or even compress. This is the kind of thing that tends to start as an engineer joking about having enough spare space to fit in their toy RISC-V core, and then actually doing it. Run out of space during development? Just delete it, it's only an unexpected bonus feature after all. It causes issues during testing? Permanently fuse it off and nobody will notice it was ever there. High-end chips are filled with dozens of "chicken bits" to gate off functionality they might not be able to get to work properly, so in a small company like Raspberry Pi it probably wouldn't be too hard to convince management to take the tiny additional risk in return for a significant PR possibility.