3 ms·

Accurate Models of AMD Matrix Cores

78 points by matt_d 10d ago

erichocean 9d ago
If you're an author of this, please follow up with the SME2 cores in Apple Silicon, and the AMX cores in Intel server processors.
- faiziktk 7d ago
  Yes, next in line is Intel AMX, and we also have several other architectures planned for analysis. Thanks for the suggestion!
peter_d_sherman 10d ago
>"Features of matrix multipliers differ across vendors and architectures of the same vendor [...] As a result, reproducibility of small matrix multiplier results [differences] across devices is not possible and cannot be achieved by software control. Implementation details of matrix multipliers are not documented, making it difficult to interpret discrepancies in the computed results." I'm guessing (but not knowing) that small subtle differences in matrix multiply across different vendor's architectures (and product generations of an individual vendor's architecture) is responsible for a good portion of software crashes when trying to run a local LLM on a different architecture or with a different stack (ROCm vs. CUDA, for example) than the ones it has been explicitly tested on. As such, this marks a rather significant problem for the future, which can basically be stated as: There needs to be a standard matrix multiply specification (much like IEEE-754 is/was for floating point operations) that all future vendors of AI accelerators (any GPU, CPU, NPU or IC manufacturer whose circuits implement matmul) adhere to, such that the matmul of one vendor is exactly and precisely compatible with the matmul of another. Hardware vendors of course, are free to compete in terms of speed, power efficiency, number of matmul engines on a given piece of silicon, parallelization optimizations, etc., but the basic matmul operation should be exactly and precisely compatible across vendors and across future product versions. Step 1: We need a spec for this... (Maybe IEEE is already working on one? If so, that's a good step forward!) Step 2: Hardware vendors need to implement it, to be universally compatible in all of their IC's that use matmul, in the future...
- varispeed 10d ago
  Isn't the same amongst same architectures? For instance, when I created script to train my model it worked fine on RTX 5080, but when I rented H100 to hopefully wait less for completion of training, the training would collapse just in a few epochs, suggesting they compute things differently (RTX 5080 would run thousands of epochs without collapsing. The same script and the same data).
- stymaar 10d ago
  > is responsible for a good portion of software crashes I doubt it's the case, it should result in slightly different logits and generated tokens, but it shouldn't lead to crashes. I suspect what you're facing are simply driver bugs…
  - rfgplk 10d ago
    It's memory/tiling alignment issues + wrong instruction/feaatures.
- rfgplk 10d ago
  Yep, 100%. In fact writing anything GPU co-processor related is nothing like porting CPU code. Sometimes the entire kernel needs to be rewritten outright when switching between GPU gens (of the same vendor). Things like precision et al also vary massively. Usually these architectural differences are handled by the intermediate platform layer, which often doesn't apply if you're writing low-level kernels. Although this > I'm guessing (but not knowing) that small subtle differences in matrix multiply across different vendor's architectures (and product generations of an individual vendor's architecture) is responsible for a good portion of software crashes when trying to run a local LLM on a different architecture or with a different stack (ROCm vs. CUDA, for example) than the ones it has been explicitly tested on. Has to do with everything else but matrix mult precision. Feature support/drivers/alignment generally causes crashes, and again, the GPU field situation is so precarious that it's 10x worse than the AVX512 segmentation in the CPU world. You basically need to microverify whether the target GPU supports a given instruction/feature.
- kmeisthax 9d ago
ArashEdalat 10d ago
Worked in the GPU/TPU validation at Google, and this tracks with something we ran into constantly: pinning down raw matrix-core throughput at the instruction level is necessary but not sufficient. The divergence between synthetic and production numbers we kept hitting wasn't from ALU throughput — it was memory bandwidth contention once multiple kernels shared HBM, and thermal throttling on sustained runs that never shows up in short burst benchmarks. A model like this would need a sustained-load / multi-tenant term to match what we actually measured in prod. Also relevant to varispeed's RTX5080-vs-H100 collapse above — divergence that only shows up over many epochs, not the first few, usually points to accumulated numerical or thermal drift rather than a single wrong instruction.

78 points by matt_d 10d ago

If you're an author of this, please follow up with the SME2 cores in Apple Silicon, and the AMX cores in Intel server processors.

faiziktk 7d ago
Yes, next in line is Intel AMX, and we also have several other architectures planned for analysis. Thanks for the suggestion!

peter_d_sherman 10d ago

>"Features of matrix multipliers differ across vendors and architectures of the same vendor [...] As a result, reproducibility of small matrix multiplier results [differences] across devices is not possible and cannot be achieved by software control. Implementation details of matrix multipliers are not documented, making it difficult to interpret discrepancies in the computed results." I'm guessing (but not knowing) that small subtle differences in matrix multiply across different vendor's architectures (and product generations of an individual vendor's architecture) is responsible for a good portion of software crashes when trying to run a local LLM on a different architecture or with a different stack (ROCm vs. CUDA, for example) than the ones it has been explicitly tested on. As such, this marks a rather significant problem for the future, which can basically be stated as: There needs to be a standard matrix multiply specification (much like IEEE-754 is/was for floating point operations) that all future vendors of AI accelerators (any GPU, CPU, NPU or IC manufacturer whose circuits implement matmul) adhere to, such that the matmul of one vendor is exactly and precisely compatible with the matmul of another. Hardware vendors of course, are free to compete in terms of speed, power efficiency, number of matmul engines on a given piece of silicon, parallelization optimizations, etc., but the basic matmul operation should be exactly and precisely compatible across vendors and across future product versions. Step 1: We need a spec for this... (Maybe IEEE is already working on one? If so, that's a good step forward!) Step 2: Hardware vendors need to implement it, to be universally compatible in all of their IC's that use matmul, in the future...

varispeed 10d ago
Isn't the same amongst same architectures? For instance, when I created script to train my model it worked fine on RTX 5080, but when I rented H100 to hopefully wait less for completion of training, the training would collapse just in a few epochs, suggesting they compute things differently (RTX 5080 would run thousands of epochs without collapsing. The same script and the same data).
stymaar 10d ago
> is responsible for a good portion of software crashes I doubt it's the case, it should result in slightly different logits and generated tokens, but it shouldn't lead to crashes. I suspect what you're facing are simply driver bugs…
- rfgplk 10d ago
  It's memory/tiling alignment issues + wrong instruction/feaatures.
rfgplk 10d ago
Yep, 100%. In fact writing anything GPU co-processor related is nothing like porting CPU code. Sometimes the entire kernel needs to be rewritten outright when switching between GPU gens (of the same vendor). Things like precision et al also vary massively. Usually these architectural differences are handled by the intermediate platform layer, which often doesn't apply if you're writing low-level kernels. Although this > I'm guessing (but not knowing) that small subtle differences in matrix multiply across different vendor's architectures (and product generations of an individual vendor's architecture) is responsible for a good portion of software crashes when trying to run a local LLM on a different architecture or with a different stack (ROCm vs. CUDA, for example) than the ones it has been explicitly tested on. Has to do with everything else but matrix mult precision. Feature support/drivers/alignment generally causes crashes, and again, the GPU field situation is so precarious that it's 10x worse than the AVX512 segmentation in the CPU world. You basically need to microverify whether the target GPU supports a given instruction/feature.
kmeisthax 9d ago

ArashEdalat 10d ago

Worked in the GPU/TPU validation at Google, and this tracks with something we ran into constantly: pinning down raw matrix-core throughput at the instruction level is necessary but not sufficient. The divergence between synthetic and production numbers we kept hitting wasn't from ALU throughput — it was memory bandwidth contention once multiple kernels shared HBM, and thermal throttling on sustained runs that never shows up in short burst benchmarks. A model like this would need a sustained-load / multi-tenant term to match what we actually measured in prod. Also relevant to varispeed's RTX5080-vs-H100 collapse above — divergence that only shows up over many epochs, not the first few, usually points to accumulated numerical or thermal drift rather than a single wrong instruction.