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Abstract at IEDM website below ABSTRACT A14 NanoFlexTM Pro platform technology features the world’s smallest SRAM with a cell size <0.017μm2 and highest SRAM m

Abstract at IEDM website below ABSTRACT A14 NanoFlexTM Pro platform technology features the world’s smallest SRAM with a cell size <0.017μm2 and highest SRAM macro density to date through dimensional ground rule scaling. Coupled with standard cell innovations, it delivers a full-node PPA improvement over the predecessor N2 technology for a 10~15% speed enhancement, a 25~30% power reduction and a chip density increase by ~20% driven by logic and SRAM scaling. Key features, such as TSV, innovative RDL that enables SoIC bond pitch of 4.5μm and high-performance MiM processes, have also been developed to accelerate the system-level integration and scaling for SoIC products. Supported by robust yield and device progress, A14 technology is on track for volume production in 2028.

nwah1 19d ago
In simpler terms, the SRAM density improved by 2.9% (according to ChatGPT). Which is better than it sounds, because SRAM had reached a wall, in terms of density gains, and, chips can be dominated by SRAM in terms of surface area, so this can mean a lot more room for logic, even though that is also getting considerably denser.
- anamax 19d ago
  There's some hope of smaller SRAM in the future - https://raaam-tech.com/technology/ https://raaam-tech.com/technology/ is a three-transistor SRAM.
  - randomblock1 17d ago
    It's not quite SRAM, it needs to be refreshed like DRAM. That's the main downside compared to SRAM but it's still very interesting.
    - choilive 17d ago
      Yes, the density vs power tradeoff could make a lot of sense in a few applications.
      - MBCook 17d ago
        I wonder if it would start to make sense for SRAM caches to shrink (or not grow as fast) in favor of adding on chip DRAM cache at some tier.
        sroussey 17d ago
        Or AMD’s putting sram on a separate chip. I’m surprised they didn’t go there yet except for extra L3 instead of all of it. At some point the costs will shift the decisions.
      - kvemkon 17d ago
        They claim win + win*10: > provides up-to 50% area reduction and reduced power consumption by a factor ten
- aurareturn 16d ago
  This is exactly why Cerebras wafer chips aren’t even on N3. They stayed on N5. It is also why they are now stacking HBM onto the chip.

nwah1 19d ago

In simpler terms, the SRAM density improved by 2.9% (according to ChatGPT). Which is better than it sounds, because SRAM had reached a wall, in terms of density gains, and, chips can be dominated by SRAM in terms of surface area, so this can mean a lot more room for logic, even though that is also getting considerably denser.

anamax 19d ago
There's some hope of smaller SRAM in the future - https://raaam-tech.com/technology/ https://raaam-tech.com/technology/ is a three-transistor SRAM.
- randomblock1 17d ago
  It's not quite SRAM, it needs to be refreshed like DRAM. That's the main downside compared to SRAM but it's still very interesting.
  - choilive 17d ago
    Yes, the density vs power tradeoff could make a lot of sense in a few applications.
    - MBCook 17d ago
      I wonder if it would start to make sense for SRAM caches to shrink (or not grow as fast) in favor of adding on chip DRAM cache at some tier.
      - sroussey 17d ago
        Or AMD’s putting sram on a separate chip. I’m surprised they didn’t go there yet except for extra L3 instead of all of it. At some point the costs will shift the decisions.
    - kvemkon 17d ago
      They claim win + win*10: > provides up-to 50% area reduction and reduced power consumption by a factor ten
aurareturn 16d ago
This is exactly why Cerebras wafer chips aren’t even on N3. They stayed on N5. It is also why they are now stacking HBM onto the chip.