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TSMC revealing details about next gen A14 node
- osnium123 20d agoAbstract at IEDM website below ABSTRACT A14 NanoFlexTM Pro platform technology features the world’s smallest SRAM with a cell size <0.017μm2 and highest SRAM macro density to date through dimensional ground rule scaling. Coupled with standard cell innovations, it delivers a full-node PPA improvement over the predecessor N2 technology for a 10~15% speed enhancement, a 25~30% power reduction and a chip density increase by ~20% driven by logic and SRAM scaling. Key features, such as TSV, innovative RDL that enables SoIC bond pitch of 4.5μm and high-performance MiM processes, have also been developed to accelerate the system-level integration and scaling for SoIC products. Supported by robust yield and device progress, A14 technology is on track for volume production in 2028.
- nwah1 20d agoIn simpler terms, the SRAM density improved by 2.9% (according to ChatGPT). Which is better than it sounds, because SRAM had reached a wall, in terms of density gains, and, chips can be dominated by SRAM in terms of surface area, so this can mean a lot more room for logic, even though that is also getting considerably denser.
- anamax 19d agoThere's some hope of smaller SRAM in the future - https://raaam-tech.com/technology/ https://raaam-tech.com/technology/ is a three-transistor SRAM.
- randomblock1 18d agoIt's not quite SRAM, it needs to be refreshed like DRAM. That's the main downside compared to SRAM but it's still very interesting.
- choilive 18d agoYes, the density vs power tradeoff could make a lot of sense in a few applications.
- MBCook 18d agoI wonder if it would start to make sense for SRAM caches to shrink (or not grow as fast) in favor of adding on chip DRAM cache at some tier.
- sroussey 17d agoOr AMD’s putting sram on a separate chip. I’m surprised they didn’t go there yet except for extra L3 instead of all of it. At some point the costs will shift the decisions.
- kvemkon 17d agoThey claim win + win*10: > provides up-to 50% area reduction and reduced power consumption by a factor ten
- aurareturn 17d agoThis is exactly why Cerebras wafer chips aren’t even on N3. They stayed on N5. It is also why they are now stacking HBM onto the chip.
- surcap526 20d ago[dead]
- faceloss 20d ago[dead]
- osnium123 17d agoThat’s why TSMC is indispensable for the global economy. No other foundry can produce advanced logic at scale like them.
- aurareturn 17d agoThey are extremely reliable.
- deleted 19d ago[deleted]
- aurareturn 19d agoChip density increase is slowing down. Since N10, density scaling has been 60-80%. N3 to N2 is only 20%. And now N2 to A14 is also only 20%.
- osnium123 19d agoIs the increase in wafer cost higher than the density increase? If so, that means that the cost per transistor is also going up.
- aurareturn 19d agoIt's hard to tell because AI has pushed up costs. IE. Chip fab margins are increasing. But generally, I think it's even or increasing $/transistor for each node. I'd guess that A14 would have been 20% more expensive than N2 regardless or AI or not. It probably is still worth it because you're also getting 20-30% better power efficiency - which is a big deal for data center chips.
- xenadu02 17d agoIf we exclude short-term shortages then no. The cost to make a wafer hasn't really changed. Larger wafers improved costs but that's about it AFAIK. Feature sizes have been shrinking unevenly for two decades now combined with the overall slowdown in improvements. Transistors themselves are FinFET geometry and something like 15-30 atoms thick and maybe 80-100 across. There ain't much juice left to squeeze in terms of size but perhaps we'll figure out how to reduce leakage (heat). Physics hates the very large and the very small. The large get the tyranny of volume scaling + general relativity. The small have their entire concept of reality smashed by quantum mechanics.
- HarHarVeryFunny 17d agoThe cost-per-transistor used to fall as density increased (Moore's Law), but has now basically flattened off. As each generation of lithography tech (DUV -> EUV -> High-NA EUV) gets pushed to the limit, it becomes necessary to use multiple etching steps per layer (higher cost, less wafers-per-minute) where previously one had been enough, then the next generation (e.g. EUV vs DUV) resets that to one step, then that becomes two ... The trouble is that each new generation of tech costs considerably more than the one it replaces, both in terms of machine cost and operational cost, so the overall trend seems to have become fairly flat.
- ginko 18d agoCome on we're in the 21st century, UTF-8 is pervasive. Just call it "Å14" node.
- celsoazevedo 18d agoI don't think it's a UTF-8 problem. It's just that most people don't have "Å" on their keyboard.
- agumonkey 18d agotips in linux, remap altgr to compose and enjoy glyphs
- fastball 17d agoOn mac this is just Opt + A
- xdennis 17d agoMost people don’t have “é” on their keyboard, yet they still spell “fiancée”.
- mdp2021 17d ago> most people don't have Many people don't know. cat /usr/share/X11/locale/en_US.UTF-8/Compose | grep Å <dead_abovering> <A> : "Å" Aring # LATIN CAPITAL LETTER A WITH RING ABOVE <Multi_key> <o> <A> : "Å" Aring # LATIN CAPITAL LETTER A WITH RING ABOVE <Multi_key> <asterisk> <A> : "Å" Aring # LATIN CAPITAL LETTER A WITH RING ABOVE <Multi_key> <A> <asterisk> : "Å" Aring # LATIN CAPITAL LETTER A WITH RING ABOVE <Multi_key> <A> <A> : "Å" Aring # LATIN CAPITAL LETTER A WITH RING ABOVE
- deleted 18d ago[deleted]
- JumpCrisscross 18d agoTSMC: https://www.tsmc.com/english/dedicatedFoundry/technology/logic/l_A14 https://www.tsmc.com/english/dedicatedFoundry/technology/log... Not sure what this source is, but it looks sketchy.
- osnium123 18d agoThe source is the IEDM conference website where TSMC will be presenting the paper in Dec 2026
- dgfl 18d agoIEDM is more or less the most prestigious conference on semiconductor devices. Hard to get a more reliable source than a TSCM-affiliated paper from IEDM.
- JumpCrisscross 18d agoSorry, I got thrown off by the domain.
- moeadham 17d agoI can’t believe we’re talking Angstroms already.
- FlowingRiver 17d agoI did find it funny recently when Huawei when talking about its folded logic say the Vertical Bonding Pitch's are every 15,000 angstroms. It is a very fancy way of saying an interconnect every 1.5 microns.
- AnotherGoodName 17d agoThey should just say every 7 silicon atoms at that point.
- fc417fc802 17d ago7500 surely? But yeah at this point I feel like the diameter of a silicon atom would make for a better unit of measure.
- AnotherGoodName 17d agoOh right i was thinking the feature size (about that many namometers not microns)
- HarHarVeryFunny 17d agoWhat's wild is that the mirrors used in the EUV machines are smooth to a level of deviation even smaller that the feature size of the gates being etched. These mirrors are up to a couple of feet in diameter, with an average smoothness deviation of less than the width of an atom, maximum bump size of 1nm or less. They like to point out that if scaled up to the size of Germany (Zeiss makes them), the biggest surface defect would still only be 0.1mm!
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- AtlasBarfed 16d agoWhatever happened to the problem of electrons just hopping around since they are areas of probability rather than particles when you get small enough