4 ms·

Sounds great as a slogan, but there are no details. For comparison, Intel's 1 um process (Fab 3, 80386-era) required about 4 weeks of processing time, and if pu

Sounds great as a slogan, but there are no details. For comparison, Intel's 1 um process (Fab 3, 80386-era) required about 4 weeks of processing time, and if pushed, the samples could be processed in as little as two weeks. For a long time they were getting about one working die per 4" wafer.

LargoLasskhyfv 27d ago
They could employ something similar to https://minimalfab.eu https://minimalfab.eu https://minimalfab.com https://minimalfab.com https://www.yokogawa.com/industries/semiconductor/minimal-fab/ https://www.yokogawa.com/industries/semiconductor/minimal-fa... These are available since about a decade, and would enable such short turnaround times for single chips.
- adrian_b 27d ago
  Short turnaround times does not mean a single day. Even an ancient 1 micron CMOS process requires something like one hundred process steps, many of which may need up to a few hours in an oven. If completely automatized, it could be done in a week for small batches, but not in a day. One day could be achieved only for semi-custom integrated circuits, where the customer only specifies the interconnection of the components existing on the pre-processed chip. Decades ago, when unlike today, there were a very great number of integrated circuit producers, there were many who offered a set of IC dies from which to choose one, where each variant could have different sizes, while including various mixtures of digital gates and analog components like amplifiers, comparators, voltage references etc., and after choosing one of the available base dies the customer would specify only how to interconnect the components and how to bond the die to the package pads. With such semi-custom integrated circuits, it would be possible to complete their fabrication process in a day, by using direct exposure, instead of masks, for the final metal layers. At the 1 micron level, the photoresist can be patterned directly with a laser projector. There is no need for an electron-beam machine, like for nanometer-resolution lithography.
  - LargoLasskhyfv 27d ago
    Yes, Yes. I know. Because of that I said 'something similar'. Yokogawa/Minimal.fab themselves say different things for different chips, up to one week, but also one day. That depends on the used substrate, they don't only have the ones which are in common use. They also don't need masks for anything, and their wafers are small. It's all a little hard to get, and the most current information is their Japanese site, with translation. Have you looked deeper at theirs, or 'similar' stuff? I think it's misleading trying to extrapolate from an ancient process to this, 'or similar', because the roads taken by the mainstream(machinery and processing) do not necessarily apply to other roads, which others may have taken. And I don't mean by circumventing physics. Just applying them differently. For different volumes and scales.
    - adrian_b 27d ago
      > They also don't need masks for anything To skip the use of masks, there exists only 2 possibilities. For low resolutions, down to around the 1 micrometer claimed in the linked site, it is possible to use a small and low cost laser projector, which is also quite fast. For higher resolutions, an electron-beam machine is needed, which works in a vacuum chamber, and which is big, expensive and slow (the slowness is not actually due to the electron beam, but to the fact that a chip that must be made with high resolution lithography would have many more components in the same area than a chip that can be made with low resolution lithography). An electron-machine would be bigger by itself than what Yokogawa shows as being a "Minimal Fab", so I assume that Yokogawa uses a laser projector. I could not find any statement about which is their best achievable resolution, but they give an example of a circuit made with 4 micrometer gate length, so I assume that their best resolution might be around 1 micrometer, which is compatible with a laser projector. Yokogawa gives their processing time at one week, for a fabrication process with 98 steps, which is very close to what I have estimated in another posting here. Actually, I think that the company whose site is linked in this thread might have just bought some equipment from Yokogawa, as that could match their claims. Nonetheless, a one-day processing remains compatible only with semi-custom chips, where the customer just interconnects the pre-existing components, not with a fully custom chip. Moreover, the Yokogawa equipment uses tiny wafers, where the maximum die size is limited to about 8 by 8 millimeters, and at that size you would get 1 die per wafer, with great chances that it may be a bad one, or if you make small 2 by 2 mm dies, you get just 16 per wafer, from which a dozen might be good, and so on. So you must need only a small number of dies, otherwise the fabrication could take forever. Nonetheless, even such a small number of dies could be good enough for prototypes or for the needs of small businesses or individuals. I certainly would like to order such integrated circuits, but for this the vendor would have first to publish the technical documentation with the characterization of the semiconductor devices that can be made with their fabrication process, to enable the customer to do simulations of their designs, before submitting one for fabrication. A one-micron resolution is intermediate between that used for the Intel 80386 processors and Intel 80486 processors, but closer to the latter. So it would certainly be good enough to make various custom circuits, which could substitute the standard microcontrollers or FPGAs together with any needed auxiliary ICs, where MCUs and FPGAs typically must include at least an order of magnitude more internal resources than are used in any single project, in order to enable their use in any of those projects, so a dedicated chip can be made much simpler and more energy-efficient.
- nfjesifb 13d ago
  Right now I am working out of university labs (columbia nano initiative and berkeley nano lab) instead of buying and operating a bunch of equipment myself. These academic labs are well suited to running fast processes, doing rapid process development/validation, learning new stuff, and many are surprisingly inexpensive. berkeley specifically has a lot of dedicated MOS equipment and other resources like the baselines (linked below) which give me a helpful basis for my work. https://nanolab.berkeley.edu/public/process/baseline/ https://nanolab.berkeley.edu/public/process/baseline/
adrian_b 27d ago
Yes, only one day of processing is impossible for any kind of integrated circuit. One day of processing would be possible only for semi-custom integrated circuits, like gate arrays, which have already been fabricated until a last step that only adds one or two custom metal layers to interconnect the existing components and then separates and packages the devices. Even with that, one day of processing would be possible only for making a small number of chips, where the metal layers would be patterned without masks, by direct exposure of the photoresist with a laser projector. Making photolithography masks would take more than one day.
- gfdhjd3 26d ago
  [dead]
- nfjesifb 13d ago
  This is not unilaterally true if the devices are simple enough and make process engineering decisions specifically toward the objective of speed. I am not working on gate arrays and have made NMOS from a virgin p-type wafer in 8hrs. Some ways you can be fast: - Stock pre implanted wafers with oxide and polysilicon layers grown/deposited in advance to avoid any long furnace cycles at fabrication time. -Use spin on dopant with rapid thermal anneal furnaces instead of sending wafer to external services for implant whenever possible - Use SOI wafer and mesa isolation instead of more complicated and time intensive STI or LOCOS techniques - SOI also gives you the ability to do work function engineering that could allow for junctionless devices, further minimizing need for implant/doping steps because you don't need to form wells in oppositely doped bulk silicon - Instead of exclusively relying maskless lithography, which inherently means your exposures have to be done in sequence, you can instead rely on a combination of maskless and masked lithography so that as soon as you receive an order, you can start fabrication immediately by doing the first layer on a maskless setup while initiating mask writes for all subsequent layers in parallel across multiple mask writers. This parallelizes the lithography of every layer. I am happy to talk more specifically if there is any feedback or questions about these points. AMA.
nfjesifb 13d ago
Lots of details coming by EOD. To a new page on gothamsilicon.com

LargoLasskhyfv 27d ago

They could employ something similar to https://minimalfab.eu https://minimalfab.eu https://minimalfab.com https://minimalfab.com https://www.yokogawa.com/industries/semiconductor/minimal-fab/ https://www.yokogawa.com/industries/semiconductor/minimal-fa... These are available since about a decade, and would enable such short turnaround times for single chips.

adrian_b 27d ago
Short turnaround times does not mean a single day. Even an ancient 1 micron CMOS process requires something like one hundred process steps, many of which may need up to a few hours in an oven. If completely automatized, it could be done in a week for small batches, but not in a day. One day could be achieved only for semi-custom integrated circuits, where the customer only specifies the interconnection of the components existing on the pre-processed chip. Decades ago, when unlike today, there were a very great number of integrated circuit producers, there were many who offered a set of IC dies from which to choose one, where each variant could have different sizes, while including various mixtures of digital gates and analog components like amplifiers, comparators, voltage references etc., and after choosing one of the available base dies the customer would specify only how to interconnect the components and how to bond the die to the package pads. With such semi-custom integrated circuits, it would be possible to complete their fabrication process in a day, by using direct exposure, instead of masks, for the final metal layers. At the 1 micron level, the photoresist can be patterned directly with a laser projector. There is no need for an electron-beam machine, like for nanometer-resolution lithography.
- LargoLasskhyfv 27d ago
  Yes, Yes. I know. Because of that I said 'something similar'. Yokogawa/Minimal.fab themselves say different things for different chips, up to one week, but also one day. That depends on the used substrate, they don't only have the ones which are in common use. They also don't need masks for anything, and their wafers are small. It's all a little hard to get, and the most current information is their Japanese site, with translation. Have you looked deeper at theirs, or 'similar' stuff? I think it's misleading trying to extrapolate from an ancient process to this, 'or similar', because the roads taken by the mainstream(machinery and processing) do not necessarily apply to other roads, which others may have taken. And I don't mean by circumventing physics. Just applying them differently. For different volumes and scales.
  - adrian_b 27d ago
    > They also don't need masks for anything To skip the use of masks, there exists only 2 possibilities. For low resolutions, down to around the 1 micrometer claimed in the linked site, it is possible to use a small and low cost laser projector, which is also quite fast. For higher resolutions, an electron-beam machine is needed, which works in a vacuum chamber, and which is big, expensive and slow (the slowness is not actually due to the electron beam, but to the fact that a chip that must be made with high resolution lithography would have many more components in the same area than a chip that can be made with low resolution lithography). An electron-machine would be bigger by itself than what Yokogawa shows as being a "Minimal Fab", so I assume that Yokogawa uses a laser projector. I could not find any statement about which is their best achievable resolution, but they give an example of a circuit made with 4 micrometer gate length, so I assume that their best resolution might be around 1 micrometer, which is compatible with a laser projector. Yokogawa gives their processing time at one week, for a fabrication process with 98 steps, which is very close to what I have estimated in another posting here. Actually, I think that the company whose site is linked in this thread might have just bought some equipment from Yokogawa, as that could match their claims. Nonetheless, a one-day processing remains compatible only with semi-custom chips, where the customer just interconnects the pre-existing components, not with a fully custom chip. Moreover, the Yokogawa equipment uses tiny wafers, where the maximum die size is limited to about 8 by 8 millimeters, and at that size you would get 1 die per wafer, with great chances that it may be a bad one, or if you make small 2 by 2 mm dies, you get just 16 per wafer, from which a dozen might be good, and so on. So you must need only a small number of dies, otherwise the fabrication could take forever. Nonetheless, even such a small number of dies could be good enough for prototypes or for the needs of small businesses or individuals. I certainly would like to order such integrated circuits, but for this the vendor would have first to publish the technical documentation with the characterization of the semiconductor devices that can be made with their fabrication process, to enable the customer to do simulations of their designs, before submitting one for fabrication. A one-micron resolution is intermediate between that used for the Intel 80386 processors and Intel 80486 processors, but closer to the latter. So it would certainly be good enough to make various custom circuits, which could substitute the standard microcontrollers or FPGAs together with any needed auxiliary ICs, where MCUs and FPGAs typically must include at least an order of magnitude more internal resources than are used in any single project, in order to enable their use in any of those projects, so a dedicated chip can be made much simpler and more energy-efficient.
nfjesifb 13d ago
Right now I am working out of university labs (columbia nano initiative and berkeley nano lab) instead of buying and operating a bunch of equipment myself. These academic labs are well suited to running fast processes, doing rapid process development/validation, learning new stuff, and many are surprisingly inexpensive. berkeley specifically has a lot of dedicated MOS equipment and other resources like the baselines (linked below) which give me a helpful basis for my work. https://nanolab.berkeley.edu/public/process/baseline/ https://nanolab.berkeley.edu/public/process/baseline/

adrian_b 27d ago

Yes, only one day of processing is impossible for any kind of integrated circuit. One day of processing would be possible only for semi-custom integrated circuits, like gate arrays, which have already been fabricated until a last step that only adds one or two custom metal layers to interconnect the existing components and then separates and packages the devices. Even with that, one day of processing would be possible only for making a small number of chips, where the metal layers would be patterned without masks, by direct exposure of the photoresist with a laser projector. Making photolithography masks would take more than one day.

gfdhjd3 26d ago
[dead]
nfjesifb 13d ago
This is not unilaterally true if the devices are simple enough and make process engineering decisions specifically toward the objective of speed. I am not working on gate arrays and have made NMOS from a virgin p-type wafer in 8hrs. Some ways you can be fast: - Stock pre implanted wafers with oxide and polysilicon layers grown/deposited in advance to avoid any long furnace cycles at fabrication time. -Use spin on dopant with rapid thermal anneal furnaces instead of sending wafer to external services for implant whenever possible - Use SOI wafer and mesa isolation instead of more complicated and time intensive STI or LOCOS techniques - SOI also gives you the ability to do work function engineering that could allow for junctionless devices, further minimizing need for implant/doping steps because you don't need to form wells in oppositely doped bulk silicon - Instead of exclusively relying maskless lithography, which inherently means your exposures have to be done in sequence, you can instead rely on a combination of maskless and masked lithography so that as soon as you receive an order, you can start fabrication immediately by doing the first layer on a maskless setup while initiating mask writes for all subsequent layers in parallel across multiple mask writers. This parallelizes the lithography of every layer. I am happy to talk more specifically if there is any feedback or questions about these points. AMA.

nfjesifb 13d ago

Lots of details coming by EOD. To a new page on gothamsilicon.com