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What happens when a GPU reads memory
- empiricus 2mo agoFor a long time, the chip manufacturers had an inclination to simplify the hardware and rely on the software adapting and optimizing. But for decades this bid failed. Now we have the unrelenting AI capable of finetuning kernels relatively quickly. Maybe simpler hw will work this time? Note: not sure if TPU/NPU is not only simple but also too limited.
- ahartmetz 2mo agoI have some doubts. For example, there is no software replacement for out-of-order execution: It is unknown before runtime in which cache level the required data will be or which values it will have (which changes the latency of a few instructions).
- Retr0id 2mo agoWhat if caching was not transparent, but required explicit management?
- frogblast 2mo agoThat was the PS3 SPU. It was very fast for its time, but only for the small subset of code that could work within its constraints, and viciously difficult to program for.
- rasz 2mo agoWe tried that, doesnt work out in general computers running more than one task. DSPs do that, Atari Jaguar, Sony PS2 and PS3 did, all the GPUs manually manage cache. More than one task and you start a fight over resources, have to manage hierarchies, priorities, all the stuff that now happens automagically.
- asrgianewrion 2mo ago[dead]
- yipinwong 2mo agoThis is a type of article that is HN worthy and came to HN for initially because I don't even understand a third of content there. Giving me inspiration to dive deeper. SEriously, I don't understand it (yet) lol.
- nazgulsenpai 2mo agoThat's the best feeling -- idly clicking through looking for that one rabbit hole to fall down then stumbling upon a gem like this. I noticed this the first time on copetti.org articles about game console architectures: know nothing, look every jargon or acronym up as you read along, end up with 42 tabs and a basic high-level understanding of the topic by the end.
- brcmthrowaway 2mo agoCtrl+F PCIe BAR.. nothing.
- porridgeraisin 2mo agoThis is talking about HBM/GDDR
- KK7NIL 2mo agoa.k.a. VRAM
- brcmthrowaway 2mo agoSomething needs to be transferred from sysmem right?
- wmf 2mo agoThat's probably PCIe DMA initiated by the GPU so I don't think BAR is used.
- porridgeraisin 2mo agoPcie dma uses BAR registers setup by cpu. It will contain information about the physical memory address for one. On newer systems, there is NVLINK C2C which is more tightly integrated and less general. Regardless, my point was the the article is about vram. However, there is one situation when vram access itself uses the bar, to be fair. When you do P2P dma, code (kernel, either the inbuilt version or the one in the nvidia driver) running on the cpu sets up the DMA engines's GART to contain the BAR1s of the other.
- snigacookie 2mo agoCan someone help me understand why I spent 5 minutes reading something that I still don't understand? Link for the ELI5 version?
- wmf 2mo agoThere isn't really an ELI5 version of computer architecture but you could start with the book Inside the Machine by Jon Stokes. Then you can get into SIMT.
- KellyCriterion 2mo agoVERY good article, reminds me on: "what every programmer should know about memory" https://github.com/Ty-Chen/Reading-List/blob/master/What%20every%20programmer%20should%20know%20about%20memory.pdf https://github.com/Ty-Chen/Reading-List/blob/master/What%20e...
- WalterGR 2mo agoThat’s somebody’s highlighted copy of the PDF. Here’s a clean version: https://people.freebsd.org/~lstewart/articles/cpumemory.pdf https://people.freebsd.org/~lstewart/articles/cpumemory.pdf
- mathisfun123 2mo agoYMMV; not all GPUs work exactly like this
- xyzsparetimexyz 2mo ago> Little of the detail of this path is documented by NVIDIA, at least not to the level that we’d like, so we’ll determine it by running timing experiments on the hardware itself Or you could just use the AMD isa.