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RISC-V is in many aspects just legally-distinct-MIPS, from the base instruction set all the way up to how certain extensions introduce kludges that are very rem
by spicyjpeg 2mo ago
RISC-V is in many aspects just legally-distinct-MIPS, from the base instruction set all the way up to how certain extensions introduce kludges that are very reminiscent of later MIPS additions. While I do somewhat agree on the fact it was a huge missed opportunity to improve upon MIPS's technical flaws in order to realistically compete against the likes of ARMv8, we still have to keep in mind that the primary driving force behind RISC-V is and has always been fixing the legal flaws instead.
There is indeed plenty of value to be had from a standardized (if poorly) PlayStation-1-era instruction set you can safely implement in silicon with no risk of a zombie company husk coming after you, especially in the ASIC space where (as Dmitry himself recognized) anything is better than an 8051 core you need a copy of Keil C51 and a lot of patience to write code for. Even if you end up having to add custom extensions, it still is a much better starting point than coming up with your own bespoke ISA, building a toolchain around it and convincing potential customers that your proprietary architecture is worth the effort to deal with over another vendor's licensed Cortex-M cores with full GCC and LLVM support.
- inigyou 2mo agoHas it been proven that no patent troll holds a patent covering RISC-V? Of course not because that's impossible to prove.
- wren6991 2mo agoYou might find this relevant: RISC-V Genealogy (2016) https://riscv.org/wp-content/uploads/2025/02/EECS-2016-6.pdf https://riscv.org/wp-content/uploads/2025/02/EECS-2016-6.pdf Or in poster form: https://riscv.org/wp-content/uploads/2025/02/RISC-V-Instruction-Lineage-Poster-v6.pdf https://riscv.org/wp-content/uploads/2025/02/RISC-V-Instruct...
- phire 2mo agoYeah, very much legally distinct MIPS, at least as a starting point. The biggest tell is the mnemonics. While RISC-V takes a bunch of ideas from other places, and cleans things up, it copies a lot of mnemonics straight from MIPS. But it also copies a lot of other ideas from MIPS, like the absolute distain for flag registers.
- _0ffh 2mo ago>absolute distain for flag registers It's worst aspect maybe.
- deleted 2mo ago[deleted]
- wk_end 2mo agoThe RISC-V specs insist that this is important for simplifying high performance designs, because a flag register is a single piece of shared state that instructions are constantly (and often inadvertently!) touching. This necessarily introduces hazards and serialization. I don’t know enough about high performance microarchitecture design to evaluate that argument confidently, but it seems to make sense to me.
- _0ffh 2mo agoInadvertent touching is fixable, ARM for example did it with the S bit (though on AArch64 it's slightly more complicated). I regard it as a mistake of RISC-V. The flag register was invented for good reasons, and dropping it is a trade-off I personally do not think is worth the downside.
- phire 2mo agoI don't agree with the argument. By the time you have an out-of-order core, there is already so much shared state you have to synchronise, and you have a bunch of complex mechanisms for dealing with it. Adding a flags register doesn't really add any more complexity, it's just a small bit of extra state attached to it. And we already have the solution, it's register renaming. We are already renaming all the GPRs and FPRs, and we are probably also renaming part of fscr (because turns out, RISC-V does have flags for floating point operations), maybe a few other bits of state. So we just use the existing renaming mechanism to rename a bank of flags registers; That single logical shared flags register is actually backed with a bank of non-shared physical flags registers, neatly solving all concerns. Sure, the renamed flags do take up a bit of die space. But IMO they don't add any extra design complexity, and shouldn't have any performance impact on maximum clock speed. RISC-V isn't quite as disadvantaged by the lack of flags as some might suggest (and I wouldn’t say the lack of flags is RISC-V’s worst aspect), but there are a few sequences (add-with-carry, some conditional-moves, detecting overflow) where RISC-V is forced to burn an extra instruction or two to deal with the lack of flags, and IMO eliminating that would be worth the cost of slightly more die space. Also, avoiding the need for dedicated compare-and-branch instructions would free up encoding space for other things (including larger range on branches)
- fluffybucktsnek 2mo ago> Of course not because that's impossible to prove. Why?
- hyperhello 2mo agoIt's supposed to be impossible to prove a negative. But it might still happen some day. We just don't know.
- fluffybucktsnek 2mo ago"it's impossible to prove a negative" is a simplification. A negation is just the oppositive of an affirmation. If the affirmation is "there is an element E of an infinite set S that satisfies property P", the negation would be "there is no E in S that satisfy P", which would make proving by enumeration require checking every element of an infinite set, which is impossible. But other forms of proof might be possible. The set of US patents, however, are not infinite and, IIRC, is also public. That said, IP laws are a mess.
- adastra22 2mo agoIt was a joke I think.
- inigyou 2mo agoSomeone might also file a new parent, then apply it against RISC-V. You'd think that wouldn't be allowed to happen, and maybe it isn't, but only an expensive lawsuit will prove it
- fluffybucktsnek 2mo agoGiven the nature of the US legal system as based on common law, that applies beyond patents, and may affect ARM and x86 as well. In the end, the real, effective law is the one understood by judges, adjucated in court cases, built on precedents. That being said, I don't expect someone filing a new patent after a RISC-V extension being published to last much longer beyond discovery in most cases, which should keep costs in lower end. Specially so in cases of bad faith.
- pavlov 2mo agoPatents only last 20 years. If you build your architecture on ideas that are documented to be older than twenty years, it greatly reduces the risk that a patent holder comes from nowhere: even if they did have the patent, it would have expired.
- jurgenburgen 2mo agoHow quickly does the industry move? Would there be any value in a 2006-era instruction set? How would you even start making sure you didn’t infringe on any patents that came after 2006?
- pavlov 2mo agoThe first version of RISC-V was released in 2010. It was based on work done at Berkeley in the 1980s (RISC versions one to four). One reason that RISC-V has so many optional extensions is that you can trust the core is very likely to be patent-free (because everything in it is documented to be older than 20 years) and just evaluate the extensions you need.
- u1hcw9nx 2mo agoIf you iterate trough every concept RISC-V has, you might be able to prove it. The RISC/MIPS concepts date back over 40 years. The base instruction set is intentionally designed with unencumbered, expired, or public-domain architectural concepts. RICV-V microarchitectures and implementations are at much high risk of violating patents. Especially anything that is even slightly high performance. SiFive, Andes , and Alibaba’s T-Head are filing thousands of patents on microarchitectural optimizations and extensions. China's RISC-V patent-sharing alliances and other industry groups are building defensive patent cross-license around their RISC-V-related patents.
- dreamcompiler 2mo ago> it still is a much better starting point than coming up with your own bespoke ISA 5 years ago I would have agreed with this but now I'm not so sure. We live in an era where you can tell a robot "Here's some C code. Design a 64-bit ISA, write the Verilog to implement it in an FPGA, write a C compiler for it, and use it to compile the C code I showed you earlier." And now your ISA and your compiler are part of your moat. I can just see the VCs salivating.
- water-drummer 2mo agoComing up with any ISA and coming up with a good or better ISA are two very different things.
- creato 2mo agoIf that's really all it takes, then it is not much of a moat.
- pyvpx 2mo agoIn the set of all possible working implementations, there are one or more that are novel enough to become a moat legally or otherwise. If everyone has the same power (number of tokens) then capability (experience and understanding) becomes the differentiator to “find” that moat first.
- userbinator 2mo agoit still is a much better starting point than coming up with your own bespoke ISA, building a toolchain around it and convincing potential customers that your proprietary architecture is worth the effort to deal There are lots of somewhat successful yet little-known Chinese companies with their own proprietary architectures and the toolchains to match, so I don't think it's that clear-cut. (That said, most if not all of them are somewhat MIPS/RISC-V-ish anyway...) I do think 8051 is better when you don't need 32 or even 16 bits. Even 4-bit MCUs are still around in ultra-low-cost ultra-high-volume products, which is to say RISC-V is, as you said, just a different flavour of MIPS with very similar tradeoffs.
- skew-aberration 2mo agoGoogle search turns up LoongArch (RISC), Shenwei (CUDA-like, HPC), UniCore (RISC). ESP32 is using Tensilica LX6/LX7 RISC base (RISC designed for custom hardware extensions).
- brucehoult 2mo agoC-Sky and Andes NDS32 were popular enough to be supported by both GCC and the Linux kernel, both switched to RISC-V. ESP32 switched to RISC_V for all new chips. Interestingly Synopsys's ARC's latest version ARC-V is RISC-V. I think all major FPGA vendors now offer fully supported RISC-V soft cores either alongside their older proprietary ISAs or as the latest upgrade. Several (e.g. Microchip and Gowin) have included real RISC-V cores inside FPGAs.
- petra 2mo agoChina is different - the state probably has impact on cpu/mcu vendor selection.
- t-3 2mo agoAll states regulate, subsidize, or otherwise exert influence on companies acting in their territories. China is not unique or different in that regard. They have been forced to try somewhat harder, but that was really due to the actions of the US trying to restrict their access to free trade. Chine restrictions on buying western tech didn't come until far after NATO countries had placed similar restrictions on Chinese tech.